diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-14 14:33:45 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-18 20:35:58 +0100 |
| commit | b457649ef6ab163d30d9d38521c10124b59bdddc (patch) | |
| tree | fb97ec53e1692d12294b4718604c747768ca2cf5 /src | |
| parent | a95baf9f7f625d29a50c3e25f92f1118d6c626ab (diff) | |
| download | coreboot-b457649ef6ab163d30d9d38521c10124b59bdddc.tar.xz | |
soc/intel/quark: Enumerate the PCI devices
Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/quark/chip.c | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index f14dde0b55..61c0803c5f 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -16,9 +16,10 @@ #include "chip.h" #include <console/console.h> +#include <device/device.h> #include <fsp/ramstage.h> -static void soc_init(void *chip_info) +static void chip_init(void *chip_info) { /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) @@ -27,7 +28,30 @@ static void soc_init(void *chip_info) fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); } +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void chip_enable_dev(device_t dev) +{ + const char *type_name = dev_path_name(dev->path.type); + + /* Set the operations if it is a special bus type */ + printk(BIOS_DEBUG, "type: %s\n", type_name); + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; +} + struct chip_operations soc_intel_quark_ops = { CHIP_NAME("Intel Quark") - .init = &soc_init, + .init = &chip_init, + .enable_dev = chip_enable_dev, }; |