diff options
| author | Vince Hsu <vinceh@nvidia.com> | 2014-05-16 18:07:53 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-30 21:31:32 +0100 |
| commit | b4bd53a3cba45b2cbf86b8b020bb8a678e583f97 (patch) | |
| tree | 45cb0ae9e950b0f02ac8ee5a5cf72d6694330519 /src | |
| parent | c09642e31560b63c643f4ca5a7710057b23106cd (diff) | |
| download | coreboot-b4bd53a3cba45b2cbf86b8b020bb8a678e583f97.tar.xz | |
tegra124: Active dc/sor register change immediately
When doing DP attach, we need to make sure the register change to
take effect immediately, otherwise it may fail to catch the attach
timing.
BRANCH=None
BUG=chrome-os-partner:28128
TEST=Display works and system boots up on Nyan and Big
Original-Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200414
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 47b86e2893fa667bebada6a0e0b443886dd5ee02)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf809b46e675bbdb8633d9a4f31d005d6644bd2a
Reviewed-on: http://review.coreboot.org/7951
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/nvidia/tegra124/sor.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 0e96764b60..2c059bf066 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -762,9 +762,11 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor) tegra_dc_sor_super_update(sor); /* Enable dc */ + reg_val = READL(&disp_ctrl->cmd.state_access); + WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); - WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); + WRITEL(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, |