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| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2012-10-31 15:39:51 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-07 04:02:54 +0100 |
| commit | becacec022602ae1ab876c58d8ae69092327b9fe (patch) | |
| tree | 88006694e699965ce8b777a5708d86babaf5a66c /src | |
| parent | cf81b8294b95c13b27aa9f53ca8e958699b4290c (diff) | |
| download | coreboot-becacec022602ae1ab876c58d8ae69092327b9fe.tar.xz | |
AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
Each G34 socket has two node. Previous lapic algorithm is written for
the CPU which has one node per socket. I test the code on h8qgi with
4 family 15 CPUs(8 cores per CPU). The topology is:
socket 0 --> Node 0, Node 1
socket 2 --> Node 2, Node 3
socket 1 --> Node 4, Node 5
socket 3 --> Node 6, Node 7
Each node has 4 cores.
I change the code according to this topology.
Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1659
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/agesa/family15/northbridge.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 12a211f697..78986e4a0c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1068,7 +1068,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } - u32 apic_id = (i * core_max) + j + lapicid_start; +#if CONFIG_CPU_AMD_SOCKET_G34 + u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); +#else + u32 apic_id = (i * core_max) + j + lapicid_start; +#endif printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); |