diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2017-10-12 17:22:22 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 02:13:18 +0000 |
| commit | c869cd2f44f9880e1757cb83be0aa23d351fa99c (patch) | |
| tree | 9e58996d92f93ae2d37a84d002ce95589f6a627c /src | |
| parent | caca9c7c62245add094e75288136a9436dbadfc2 (diff) | |
| download | coreboot-c869cd2f44f9880e1757cb83be0aa23d351fa99c.tar.xz | |
mb/google/fizz: skip reading SPD data when DUT resumes from S3
This patch skips SPD data reading when system resumes from S3 since
MRC cahce is adopted and validated in fsp_memory_init.
BUG=b:67021596
TEST=Run suspend/resume on Fizz and make sure the systems are
working well when system resumes from S3. Checked dmidecode
information and SMBIOS type 17 data is the same with cold
boot.
Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/fizz/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 065ecd3a8a..405c4c18b4 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -22,11 +22,16 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; /* Rcomp resistor */ const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */ const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + /* SPD was saved in S0/S5 path, skips it when resumes from S3 */ + if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME) + return; + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); |