diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-07-03 10:32:41 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-08 23:07:27 +0000 |
| commit | ca36acf773b1941c6df25329846765d0225fbd37 (patch) | |
| tree | 4322cbea15f45a21c3f6729a9ceeca79df7bfa79 /src | |
| parent | e6b415f0e3c854addb0fb19e28e19d012408d766 (diff) | |
| download | coreboot-ca36acf773b1941c6df25329846765d0225fbd37.tar.xz | |
mb/google/zork: Move GPIO_137 configuration to ramstage
This change moves the configuration of GPIO_137 to happen in ramstage
since there is nothing in coreboot that requires the state of write
protect GPIO for zork.
Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c | 6 | ||||
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c | 6 |
2 files changed, 4 insertions, 8 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index ea858195a5..8e6124c6d7 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -28,8 +28,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), /* CLK_REQ2_L - NVMe */ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), - /* BIOS_FLASH_WP_ODL */ - PAD_GPI(GPIO_137, PULL_NONE), /* USI_RESET - reset */ PAD_GPO(GPIO_140, HIGH), /* USB_HUB_RST_L - reset*/ @@ -57,8 +55,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = { PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), /* CLK_REQ2_L - NVMe */ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), - /* BIOS_FLASH_WP_ODL */ - PAD_GPI(GPIO_137, PULL_NONE), /* USI_RESET - reset */ PAD_GPO(GPIO_140, HIGH), /* USB_HUB_RST_L - reset*/ @@ -165,6 +161,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_132, PULL_NONE), /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ PAD_GPI(GPIO_135, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), /* USI_RESET */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 60f997de53..77a3212de5 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -26,8 +26,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), /* CLK_REQ4_L - SSD */ PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP), - /* BIOS_FLASH_WP_ODL */ - PAD_GPI(GPIO_137, PULL_NONE), /* USI_RESET - reset */ PAD_GPO(GPIO_140, HIGH), /* SD_AUX_RESET_L */ @@ -51,8 +49,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = { PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), /* CLK_REQ4_L - SSD */ PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP), - /* BIOS_FLASH_WP_ODL */ - PAD_GPI(GPIO_137, PULL_NONE), /* USI_RESET - reset */ PAD_GPO(GPIO_140, HIGH), /* SD_AUX_RESET_L */ @@ -157,6 +153,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_130, PULL_UP), /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ PAD_GPI(GPIO_135, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), /* USI_RESET */ |