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authorDamien Zammit <damien@zamaudio.com>2017-10-04 20:07:47 +1100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-10-14 08:00:34 +0000
commitd2b5b734e8d303f35f99523809e3b1044fe5f203 (patch)
treedb3ce4c04fd60a9c0ff00496b7f28239cf2da147 /src
parent66030fa5ab35ac54b2569532a36c6baacc0bde40 (diff)
downloadcoreboot-d2b5b734e8d303f35f99523809e3b1044fe5f203.tar.xz
biostar/a68n_5200: Clone amd/olivehill
Altered Kconfig board names to make it pass lint Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/biostar/a68n_5200/BiosCallOuts.c182
-rw-r--r--src/mainboard/biostar/a68n_5200/Kconfig62
-rw-r--r--src/mainboard/biostar/a68n_5200/Kconfig.name2
-rw-r--r--src/mainboard/biostar/a68n_5200/Makefile.inc22
-rw-r--r--src/mainboard/biostar/a68n_5200/OemCustomize.c152
-rw-r--r--src/mainboard/biostar/a68n_5200/OptionsIds.h59
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl110
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/gpe.asl74
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/ide.asl246
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/mainboard.asl35
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/routing.asl193
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/sata.asl146
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/si.asl23
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/sleep.asl93
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/superio.asl0
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/thermal.asl0
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl128
-rw-r--r--src/mainboard/biostar/a68n_5200/acpi_tables.c52
-rw-r--r--src/mainboard/biostar/a68n_5200/board_info.txt1
-rw-r--r--src/mainboard/biostar/a68n_5200/buildOpts.c342
-rw-r--r--src/mainboard/biostar/a68n_5200/cmos.layout66
-rw-r--r--src/mainboard/biostar/a68n_5200/devicetree.cb72
-rw-r--r--src/mainboard/biostar/a68n_5200/dsdt.asl87
-rw-r--r--src/mainboard/biostar/a68n_5200/irq_tables.c101
-rw-r--r--src/mainboard/biostar/a68n_5200/mainboard.c29
-rw-r--r--src/mainboard/biostar/a68n_5200/mptable.c228
-rw-r--r--src/mainboard/biostar/a68n_5200/romstage.c54
27 files changed, 2559 insertions, 0 deletions
diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
new file mode 100644
index 0000000000..0ff1e9a700
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include "FchPlatform.h"
+#include "cbfs.h"
+#include "imc.h"
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * AMD Olivehill Platform ALC272 Verb Table
+ */
+static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
+ {0x11, 0x411111F0}, // - SPDIF_OUT2
+ {0x12, 0x411111F0}, // - DMIC_1/2
+ {0x13, 0x411111F0}, // - DMIC_3/4
+ {0x14, 0x411111F0}, // Port D - LOUT1
+ {0x15, 0x411111F0}, // Port A - LOUT2
+ {0x16, 0x411111F0}, //
+ {0x17, 0x411111F0}, // Port H - MONO
+ {0x18, 0x01a19840}, // Port B - MIC1
+ {0x19, 0x411111F0}, // Port F - MIC2
+ {0x1a, 0x01813030}, // Port C - LINE1
+ {0x1b, 0x411111F0}, // Port E - LINE2
+ {0x1d, 0x40130605}, // - PCBEEP
+ {0x1e, 0x01441120}, // - SPDIF_OUT1
+ {0x21, 0x01214010}, // Port I - HPOUT
+ {0xff, 0xffffffff}
+};
+
+static const CODEC_TBL_LIST OlivehillCodecTableList[] =
+{
+ {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+#define FAN_INPUT_INTERNAL_DIODE 0
+#define FAN_INPUT_TEMP0 1
+#define FAN_INPUT_TEMP1 2
+#define FAN_INPUT_TEMP2 3
+#define FAN_INPUT_TEMP3 4
+#define FAN_INPUT_TEMP0_FILTER 5
+#define FAN_INPUT_ZERO 6
+#define FAN_INPUT_DISABLED 7
+
+#define FAN_AUTOMODE (1 << 0)
+#define FAN_LINEARMODE (1 << 1)
+#define FAN_STEPMODE ~(1 << 1)
+#define FAN_POLARITY_HIGH (1 << 2)
+#define FAN_POLARITY_LOW ~(1 << 2)
+
+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
+#define FREQ_28KHZ 0x0
+#define FREQ_25KHZ 0x1
+#define FREQ_23KHZ 0x2
+#define FREQ_21KHZ 0x3
+#define FREQ_29KHZ 0x4
+#define FREQ_18KHZ 0x5
+#define FREQ_100HZ 0xF7
+#define FREQ_87HZ 0xF8
+#define FREQ_58HZ 0xF9
+#define FREQ_44HZ 0xFA
+#define FREQ_35HZ 0xFB
+#define FREQ_29HZ 0xFC
+#define FREQ_22HZ 0xFD
+#define FREQ_14HZ 0xFE
+#define FREQ_11HZ 0xFF
+
+/* Olivehill Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM failed to read the input temperture vi I2C,
+ * if other software switch the I2C switch by mistake or intention.
+ * We recommend to using IMC to control Fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ /* Enable IMC fan control. the recommand way */
+ if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ imc_reg_init();
+
+ /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
+
+ FchParams->Imc.ImcEnable = TRUE;
+ FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+
+ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
+
+ /* Thermal Zone Parameter */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
+
+ /* IMC Fan Policy temperature thresholds */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
+
+ /* IMC Fan Policy PWM Settings */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
+
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
+
+ /* NOTE:
+ * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
+ * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
+ * so we remove it from AGESA code. Please Seee FchInitLateHwm.
+ */
+ } else {
+ /* HWM fan control, the way not recommand */
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
+ }
+}
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);
+
+ /* Fan Control */
+ oem_fan_control(FchParams_env);
+}
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig
new file mode 100644
index 0000000000..55dfb11d73
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/Kconfig
@@ -0,0 +1,62 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_BIOSTAR_A68N5200
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY16_KB
+ select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+ select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_4096
+ select GFXUMA
+
+config MAINBOARD_DIR
+ string
+ default biostar/a68n_5200
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A68N5200"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
+endif # BOARD_BIOSTAR_A68N5200
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name
new file mode 100644
index 0000000000..52a7f1511a
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_BIOSTAR_A68N5200
+ bool "A68N-5200"
diff --git a/src/mainboard/biostar/a68n_5200/Makefile.inc b/src/mainboard/biostar/a68n_5200/Makefile.inc
new file mode 100644
index 0000000000..f8895faa92
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c
new file mode 100644
index 0000000000..9ed7cee723
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include <PlatformMemoryConfiguration.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = FALSE;
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS(LAYERS_4),
+
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/biostar/a68n_5200/OptionsIds.h b/src/mainboard/biostar/a68n_5200/OptionsIds.h
new file mode 100644
index 0000000000..eaf2442651
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl
new file mode 100644
index 0000000000..aa941ba9ae
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+//BTDC Due to IMC Fan, ACPI control codes
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl
new file mode 100644
index 0000000000..9a8469832b
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/biostar/a68n_5200/acpi/ide.asl b/src/mainboard/biostar/a68n_5200/acpi/ide.asl
new file mode 100644
index 0000000000..e7f4625506
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/ide.asl
@@ -0,0 +1,246 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No IDE functionality */
+
+#if 0
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "ide.asl"
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ /* save total time of primary PIO master timing to PIO spd0 */
+ Store(GTTM(PPTM), PSD0)
+ /* save total time of primary PIO slave Timing to PIO spd1 */
+ Store(GTTM(PPTS), PSD1)
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
+#endif
diff --git a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl
new file mode 100644
index 0000000000..68609d868e
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+}
diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl
new file mode 100644
index 0000000000..7cb7a2f44c
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl
@@ -0,0 +1,193 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 44 },
+ Package(){0x0001FFFF, 1, 0, 45 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 24 },
+ Package(){0x0002FFFF, 1, 0, 25 },
+ Package(){0x0002FFFF, 2, 0, 26 },
+ Package(){0x0002FFFF, 3, 0, 27 },
+
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+})
+
+Name(PS2, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS2, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GFX */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 24 },
+ Package(){0x0000FFFF, 1, 0, 25 },
+ Package(){0x0000FFFF, 2, 0, 26 },
+ Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 0 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 28 },
+ Package(){0x0000FFFF, 1, 0, 29 },
+ Package(){0x0000FFFF, 2, 0, 30 },
+ Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 1 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 32 },
+ Package(){0x0000FFFF, 1, 0, 33 },
+ Package(){0x0000FFFF, 2, 0, 34 },
+ Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 2 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 36 },
+ Package(){0x0000FFFF, 1, 0, 37 },
+ Package(){0x0000FFFF, 2, 0, 38 },
+ Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 3 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 40 },
+ Package(){0x0000FFFF, 1, 0, 41 },
+ Package(){0x0000FFFF, 2, 0, 42 },
+ Package(){0x0000FFFF, 3, 0, 43 },
+})
diff --git a/src/mainboard/biostar/a68n_5200/acpi/sata.asl b/src/mainboard/biostar/a68n_5200/acpi/sata.asl
new file mode 100644
index 0000000000..6755258f4d
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/sata.asl
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No SATA functionality */
+
+#if 0
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
+#endif
diff --git a/src/mainboard/biostar/a68n_5200/acpi/si.asl b/src/mainboard/biostar/a68n_5200/acpi/si.asl
new file mode 100644
index 0000000000..292347127e
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl
new file mode 100644
index 0000000000..1225a62785
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ \_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ Store(1,USBS)
+
+ \_SB.AWAK(Arg0)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/biostar/a68n_5200/acpi/superio.asl b/src/mainboard/biostar/a68n_5200/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/superio.asl
diff --git a/src/mainboard/biostar/a68n_5200/acpi/thermal.asl b/src/mainboard/biostar/a68n_5200/acpi/thermal.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/thermal.asl
diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl
new file mode 100644
index 0000000000..acdc8f8018
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+
+/* USB Overcurrent GPEs */
+
+#if 0 /* TODO: Update for Olivehill */
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (\_GPE) {
+ Method (_L13) {
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (\_GPE) {
+ Method (_L14) {
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (\_GPE) {
+ Method (_L15) {
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (\_GPE) {
+ Method (_L16) {
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (\_GPE) {
+ Method (_L19) {
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (\_GPE) {
+ Method (_L1A) {
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (\_GPE) {
+ Method (_L17) {
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (\_GPE) {
+ Method (_L0E) {
+ }
+ }
+}
+#endif
diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c
new file mode 100644
index 0000000000..73f305a190
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/acpi_tables.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ /* TODO: Remove the hardcode */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+ 0xFEC20000, 24);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/biostar/a68n_5200/board_info.txt b/src/mainboard/biostar/a68n_5200/board_info.txt
new file mode 100644
index 0000000000..b351b8e696
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/board_info.txt
@@ -0,0 +1 @@
+Category: eval
diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c
new file mode 100644
index 0000000000..171aa48d01
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/buildOpts.c
@@ -0,0 +1,342 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+#include "AGESA.h"
+
+#define INSTALL_FT3_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
+
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+#define INSTALL_FM2_SOCKET_SUPPORT FALSE
+
+
+#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
+ #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
+ #undef INSTALL_FT3_SOCKET_SUPPORT
+ #define INSTALL_FT3_SOCKET_SUPPORT FALSE
+ #endif
+#endif
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_CDIT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 15000
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
+#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
+#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
+#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_SLEW_RATE 10000
+#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
+ // core for C-state entry requests. A value
+ // of 0 in this field specifies that the core
+ // does not trap any IO addresses for C-state entry.
+ // Values greater than 0xFFF8 results in undefined behavior.
+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYNC_FLOOD TRUE
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
+#define BLDCFG_IOMMU_SUPPORT FALSE
+#define OPTION_GFX_INIT_SVIEW FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
+
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
+#define BLDCFG_CFG_ABM_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+#ifdef PCIEX_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
+#endif
+
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
+
+
+/* Include the files that instantiate the configuration definitions. */
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+//#define DDR400_FREQUENCY 200 ///< DDR 400
+//#define DDR533_FREQUENCY 266 ///< DDR 533
+//#define DDR667_FREQUENCY 333 ///< DDR 667
+//#define DDR800_FREQUENCY 400 ///< DDR 800
+//#define DDR1066_FREQUENCY 533 ///< DDR 1066
+//#define DDR1333_FREQUENCY 667 ///< DDR 1333
+//#define DDR1600_FREQUENCY 800 ///< DDR 1600
+//#define DDR1866_FREQUENCY 933 ///< DDR 1866
+//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+//
+///* QUANDRANK_TYPE*/
+//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+//
+///* USER_MEMORY_TIMING_MODE */
+//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+//
+///* POWER_DOWN_MODE */
+//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+
+GPIO_CONTROL olivehill_gpio[] = {
+ {183, Function1, GpioIn | GpioOutEnB | PullUpB},
+ {-1}
+};
+//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+#include <PlatformInstall.h>
diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout
new file mode 100644
index 0000000000..25860f62ef
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb
new file mode 100644
index 0000000000..a027db9815
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/devicetree.cb
@@ -0,0 +1,72 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family16kb/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family16kb
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # x4 PCIe slot
+ device pci 2.2 on end # mPCIe slot
+ device pci 2.3 on end # Realtek NIC
+ device pci 2.4 on end # Edge Connector
+ device pci 2.5 on end # Edge Connector
+ end #chip northbridge/amd/agesa/family16kb
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SM
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ end # SM
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on end # LPC 0x439d
+ device pci 14.7 on end # SD
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/agesa/family16kb/root_complex
diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl
new file mode 100644
index 0000000000..e70998921c
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/dsdt.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
+
+ /* Contains the supported sleep states for this chipset */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End \_SB scope */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c
new file mode 100644
index 0000000000..e18e47842a
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c
new file mode 100644
index 0000000000..a149ee598d
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/mainboard.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c
new file mode 100644
index 0000000000..fb8a7ce08c
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/mptable.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include "southbridge/amd/agesa/hudson/hudson.h"
+
+u8 picr_data[0x54] = {
+ 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x03,0x04,0x05,0x07
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+#if 0
+ outb(0x0B, 0xCD6);
+ outb(0x02, 0xCD7);
+
+ outb(0x50, 0xCD6);
+ outb(0x1F, 0xCD7);
+
+ outb(0x48, 0xCD6);
+ outb(0xF2, 0xCD7);
+
+ //outb(0xBE, 0xCD6);
+ //outb(0x52, 0xCD7);
+
+ outb(0xED, 0xCD6);
+ outb(0x17, 0xCD7);
+
+ *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
+
+ *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
+ *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
+ *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
+ *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
+
+ *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
+ *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
+
+ *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
+ *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
+ *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
+
+ *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
+ *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
+
+ *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
+#endif
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c
new file mode 100644
index 0000000000..8190cb7711
--- /dev/null
+++ b/src/mainboard/biostar/a68n_5200/romstage.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <commonlib/loglevel.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ int i;
+ u32 val;
+
+ /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
+ * even though the register is not documented in the Kabini BKDG.
+ * Otherwise the serial output is bad code.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+ outb(0xea, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* Set LPC decode enables. */
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
+
+ hudson_lpc_port80();
+
+ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
+ for (i = 0; i < 200000; i++)
+ val = inb(0xcd6);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 06:26:28 +0000