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authorPaul Kocialkowski <contact@paulk.fr>2015-09-16 18:23:23 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-09-23 19:35:10 +0000
commitd738b1459788590e9ab21d09f32fbf2eca324412 (patch)
treea26df65ddc7567c1b32d616895e740f0273577e5 /src
parentf47f5fb4f138d234ac0ea62a2420873afa8b86dc (diff)
downloadcoreboot-d738b1459788590e9ab21d09f32fbf2eca324412.tar.xz
google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOS
When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/veyron/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
index c474bd652f..38a9ef64f8 100644
--- a/src/mainboard/google/veyron/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -85,4 +85,9 @@ config PMIC_BUS
int
default 0
+config CBFS_SIZE
+ hex
+ default 0x100000 if CHROMEOS
+ default ROM_SIZE
+
endif # BOARD_GOOGLE_VEYRON