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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-12-02 19:35:28 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-12-03 12:03:54 +0100
commitd743e0daf3de88077068c47712d4e5bf12a1732c (patch)
tree351d932e8ddf3455ff3a01bf7ad0be437f521e4d /src
parente453b9a91134eb56bf8076d72d0b89a044093753 (diff)
downloadcoreboot-d743e0daf3de88077068c47712d4e5bf12a1732c.tar.xz
mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE
The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: I0b4e99cc0d6f89f0261f26ee61b8c175a373c730 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7625 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/g505s/Kconfig4
-rw-r--r--src/mainboard/lenovo/g505s/romstage.c4
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
index fb753dceee..fc3a6ac317 100644
--- a/src/mainboard/lenovo/g505s/Kconfig
+++ b/src/mainboard/lenovo/g505s/Kconfig
@@ -68,8 +68,4 @@ config VGA_BIOS_ID
string
default "1002,990b"
-config HUDSON_LEGACY_FREE
- bool
- default y
-
endif # BOARD_LENOVO_G505S
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index 9411ac87e2..d142a9d754 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
agesawrapper_amdinitmmio();
- /* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {