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authorPiotr Król <piotr.krol@3mdeb.com>2016-05-27 12:04:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-19 10:11:13 +0100
commitdcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5 (patch)
tree8ca75267ff1c0fa136680bbe7a87dd8b58e697ee /src
parentcff3b095c2fdb7af7b6fb0a1e09c2a66c1ad1c67 (diff)
downloadcoreboot-dcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5.tar.xz
pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/pcengines/apu2/BiosCallOuts.c157
-rw-r--r--src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex264
-rw-r--r--src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex261
-rw-r--r--src/mainboard/pcengines/apu2/Kconfig91
-rw-r--r--src/mainboard/pcengines/apu2/Kconfig.name2
-rw-r--r--src/mainboard/pcengines/apu2/Makefile.inc41
-rw-r--r--src/mainboard/pcengines/apu2/OemCustomize.c121
-rw-r--r--src/mainboard/pcengines/apu2/acpi/AmdImc.asl109
-rw-r--r--src/mainboard/pcengines/apu2/acpi/gpe.asl67
-rw-r--r--src/mainboard/pcengines/apu2/acpi/mainboard.asl37
-rw-r--r--src/mainboard/pcengines/apu2/acpi/routing.asl193
-rw-r--r--src/mainboard/pcengines/apu2/acpi/si.asl23
-rw-r--r--src/mainboard/pcengines/apu2/acpi/sleep.asl95
-rw-r--r--src/mainboard/pcengines/apu2/acpi/usb_oc.asl36
-rw-r--r--src/mainboard/pcengines/apu2/acpi_tables.c56
-rw-r--r--src/mainboard/pcengines/apu2/board_info.txt6
-rw-r--r--src/mainboard/pcengines/apu2/cmos.layout74
-rw-r--r--src/mainboard/pcengines/apu2/devicetree.cb91
-rw-r--r--src/mainboard/pcengines/apu2/dsdt.asl84
-rw-r--r--src/mainboard/pcengines/apu2/gpio_ftns.c34
-rw-r--r--src/mainboard/pcengines/apu2/gpio_ftns.h59
-rw-r--r--src/mainboard/pcengines/apu2/irq_tables.c103
-rw-r--r--src/mainboard/pcengines/apu2/mainboard.c195
-rw-r--r--src/mainboard/pcengines/apu2/mptable.c166
-rw-r--r--src/mainboard/pcengines/apu2/romstage.c145
-rw-r--r--src/southbridge/amd/pi/hudson/early_setup.c18
26 files changed, 2527 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
new file mode 100644
index 0000000000..bba814412a
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include <spd_cache.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#include "imc.h"
+#endif
+#include "hudson.h"
+#include <stdlib.h>
+
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }
+
+
+/*
+ * Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM will fail to read the input temperature via I2C if other
+ * software switches the I2C address. AMD recommends using IMC
+ * to control fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = FALSE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, IMC etc.
+ */
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
+ if (StdHeader->Func == AMD_INIT_RESET) {
+ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->FchReset.SataEnable = hudson_sata_enable();
+ FchParams->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci1Enable = FALSE;
+ } else if (StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+
+ FchParams->Azalia.AzaliaEnable = AzDisable;
+
+ /* Fan Control */
+ oem_fan_control(FchParams);
+
+ /* XHCI configuration */
+ FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci1Enable = FALSE;
+
+ /* EHCI configuration */
+ FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+
+ /* sata configuration */
+ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+ FchParams->Sata.SataDevSlpPort1 = 0;
+
+ FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+ switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+ case SataRaid:
+ case SataAhci:
+ case SataAhci7804:
+ case SataLegacyIde:
+ FchParams->Sata.SataIdeMode = FALSE;
+ break;
+ case SataIde2Ahci:
+ case SataIde2Ahci7804:
+ default: /* SataNativeIde */
+ FchParams->Sata.SataIdeMode = TRUE;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
+
+
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ int index = 0;
+
+ if (info->MemChannelId > 0)
+ return AGESA_UNSUPPORTED;
+ if (info->SocketId != 0)
+ return AGESA_UNSUPPORTED;
+ if (info->DimmId != 0)
+ return AGESA_UNSUPPORTED;
+
+ /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/
+
+ u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE);
+ if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0;
+ if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1;
+
+ printk(BIOS_INFO, "Reading SPD index %d\n", index);
+
+ if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
+ die("No SPD data\n");
+
+ Status = AGESA_SUCCESS;
+#endif
+ return Status;
+}
diff --git a/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex
new file mode 100644
index 0000000000..a70db53eda
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex
@@ -0,0 +1,264 @@
+# PCEngines 2Gb 1333
+
+# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision
+# 0x13 = Revision 1.3
+13
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+03
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6.0ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+00 05
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - OEM specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+15
+
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+b6 73
+
diff --git a/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex
new file mode 100644
index 0000000000..ac6b4c6c9d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex
@@ -0,0 +1,261 @@
+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
+
+# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision -
+# 0x13 = Revision 1.3
+13
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+08
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+21
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5 ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+20 08
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+15 44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+67 94
+
+
+
+
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
new file mode 100644
index 0000000000..f09a220966
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_PCENGINES_APU2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_PI_00730F01
+ select NORTHBRIDGE_AMD_PI_00730F01
+ select SOUTHBRIDGE_AMD_PI_AVALON
+ select SUPERIO_NUVOTON_NCT5104D
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_8192
+ select SPD_CACHE
+ select HUDSON_DISABLE_IMC
+ select USE_BLOBS
+
+config MAINBOARD_DIR
+ string
+ default pcengines/apu2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PCEngines apu2"
+
+config MAX_CPUS
+ int
+ default 4
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
+config AGESA_BINARY_PI_FILE
+ string
+ default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
+
+choice
+ prompt "J19 pins 1-10"
+ default APU2_PINMUX_OFF_C
+
+config APU2_PINMUX_OFF_C
+ bool "disable"
+
+config APU2_PINMUX_GPIO0
+ bool "GPIO"
+
+config APU2_PINMUX_UART_C
+ bool "UART 0x3e8"
+
+endchoice
+
+choice
+ prompt "J19 pins 11-20"
+ default APU2_PINMUX_OFF_D
+
+config APU2_PINMUX_OFF_D
+ bool "disable"
+
+config APU2_PINMUX_GPIO1
+ bool "GPIO"
+
+config APU2_PINMUX_UART_D
+ bool "UART 0x2e8"
+
+endchoice
+
+endif # BOARD_PCENGINES_APU2
diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
new file mode 100644
index 0000000000..ab19ee4d8a
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PCENGINES_APU2
+ bool "APU2"
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
new file mode 100644
index 0000000000..e1a5f8d018
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -0,0 +1,41 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+romstage-y += gpio_ftns.c
+
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
new file mode 100644
index 0000000000..06a8f3d8af
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/AmdImc.asl b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
new file mode 100644
index 0000000000..d3bb74e31e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl
new file mode 100644
index 0000000000..cd366dcc5d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
new file mode 100644
index 0000000000..0141481d06
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl
new file mode 100644
index 0000000000..7cb7a2f44c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/routing.asl
@@ -0,0 +1,193 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 44 },
+ Package(){0x0001FFFF, 1, 0, 45 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 24 },
+ Package(){0x0002FFFF, 1, 0, 25 },
+ Package(){0x0002FFFF, 2, 0, 26 },
+ Package(){0x0002FFFF, 3, 0, 27 },
+
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+})
+
+Name(PS2, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS2, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GFX */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 24 },
+ Package(){0x0000FFFF, 1, 0, 25 },
+ Package(){0x0000FFFF, 2, 0, 26 },
+ Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 0 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 28 },
+ Package(){0x0000FFFF, 1, 0, 29 },
+ Package(){0x0000FFFF, 2, 0, 30 },
+ Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 1 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 32 },
+ Package(){0x0000FFFF, 1, 0, 33 },
+ Package(){0x0000FFFF, 2, 0, 34 },
+ Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 2 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 36 },
+ Package(){0x0000FFFF, 1, 0, 37 },
+ Package(){0x0000FFFF, 2, 0, 38 },
+ Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 3 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 40 },
+ Package(){0x0000FFFF, 1, 0, 41 },
+ Package(){0x0000FFFF, 2, 0, 42 },
+ Package(){0x0000FFFF, 3, 0, 43 },
+})
diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl
new file mode 100644
index 0000000000..292347127e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl
new file mode 100644
index 0000000000..0734c8e3c8
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ \_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* clear USB wake up signal */
+ Store(1, USBS)
+
+ \_SB.AWAK(Arg0)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
new file mode 100644
index 0000000000..1643fe7cb4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c
new file mode 100644
index 0000000000..d5ebad49d0
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi_tables.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ /* TODO: Remove the hardcode */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+ 0xFEC20000, 24);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt
new file mode 100644
index 0000000000..a69e616195
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/board_info.txt
@@ -0,0 +1,6 @@
+Board name: PC Engines APU2
+Board URL: http://www.pcengines.ch/apu2c2.htm
+Category: half
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout
new file mode 100644
index 0000000000..d83bb14d26
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/cmos.layout
@@ -0,0 +1,74 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb
new file mode 100644
index 0000000000..3c5ec81b6c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/devicetree.cb
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/pi/00730F01
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 off end # IOMMU
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 off end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
+ device pci 2.2 on end # LAN3
+ device pci 2.3 on end # LAN2
+ device pci 2.4 on end # LAN1
+ device pci 2.5 on end # mPCIe slot 1
+ device pci 8.0 on end # Platform Security Processor
+ end #chip northbridge/amd/pi/00730F01
+
+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
+ device pci 11.0 on end # SATA
+ device pci 12.0 off end # USB EHCI0 usb[0:3] not connected
+ device pci 13.0 on end # USB EHCI1 usb[4:7]
+ device pci 14.0 on end # SM
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d # SIO NCT5104D
+ register "irq_trigger_type" = "0"
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 on
+ # UART C is conditionally turned on
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.11 on
+ # UART D is conditionally turned on
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.8 off end
+ device pnp 2e.f off end
+ # GPIO0 and GPIO1 are conditionally turned on
+ device pnp 2e.007 on end
+ device pnp 2e.107 on end
+ device pnp 2e.607 off end
+ device pnp 2e.e off end
+ end # SIO NCT5104D
+ end # LPC 0x439d
+
+ device pci 14.7 on end # SD
+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
+ end #chip southbridge/amd/pi/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
new file mode 100644
index 0000000000..1fcd9054b4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/pi/00730F01/acpi/cpu.asl>
+
+ /* Contains the supported sleep states for this chipset */
+ #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/fch.asl>
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+
+ } /* End \_SB scope */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
new file mode 100644
index 0000000000..fd1fb3c9e2
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+#include "gpio_ftns.h"
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
+{
+ u8 bdata;
+ u8 *memptr;
+
+ memptr = (u8 *)(base_addr + IOMUX_OFFSET + iomux_gpio);
+ *memptr = iomux_ftn;
+
+ memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
+ bdata = *memptr;
+ bdata &= 0x07;
+ bdata |= setting; /* set direction and data value */
+ *memptr = bdata;
+}
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
new file mode 100644
index 0000000000..4f0cbaaa62
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GPIO_FTNS_H
+#define GPIO_FTNS_H
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+
+#define IOMUX_OFFSET 0xD00
+#define GPIO_OFFSET 0x1500
+
+//
+// Based on PC Engines APU2C schematics
+// http://www.pcengines.ch/schema/apu2c.pdf
+//
+#define IOMUX_GPIO_32 0x59 // MODESW
+#define IOMUX_GPIO_49 0x40 // STRAP0
+#define IOMUX_GPIO_50 0x41 // STRAP1
+#define IOMUX_GPIO_51 0x42 // PE3 Reset
+#define IOMUX_GPIO_55 0x43 // PE4 Reset
+#define IOMUX_GPIO_57 0x44 // LED1#
+#define IOMUX_GPIO_58 0x45 // LED2#
+#define IOMUX_GPIO_59 0x46 // LED3#
+#define IOMUX_GPIO_64 0x47 // PE3_WDIS
+#define IOMUX_GPIO_66 0x5B // SPKR
+#define IOMUX_GPIO_68 0x48 // PE4_WDIS
+#define IOMUX_GPIO_71 0x4D // PROCHOT
+
+#define GPIO_32 0x164 // MODESW
+#define GPIO_49 0x100 // STRAP0
+#define GPIO_50 0x104 // STRAP1
+#define GPIO_51 0x108 // PE3 Reset
+#define GPIO_55 0x10C // PE4 Reset
+#define GPIO_57 0x110 // LED1#
+#define GPIO_58 0x114 // LED2#
+#define GPIO_59 0x118 // LED3#
+#define GPIO_64 0x11C // PE3_WDIS
+#define GPIO_66 0x16C // SPKR
+#define GPIO_68 0x120 // PE4_WDIS
+#define GPIO_71 0x134 // PROCHOT
+
+#define GPIO_OUTPUT_ENABLE 23
+#define GPIO_OUTPUT_VALUE 22
+#define GPIO_PULL_DOWN_ENABLE 21
+#define GPIO_PULL_UP_ENABLE 20
+
+#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c
new file mode 100644
index 0000000000..eaeed3f8cb
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/irq_tables.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam16.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdee8, 0x2, 0xdee8, 0x3, 0xdee8, 0x4, 0xdee8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
new file mode 100644
index 0000000000..98fe8ddf4a
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <southbridge/amd/pi/hudson/pci_devs.h>
+#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
+#include <northbridge/amd/pi/00730F01/pci_devs.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#define SPD_SIZE 128
+#define PM_RTC_CONTROL 0x56
+#define PM_S_STATE_CONTROL 0xBA
+
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+#if defined(__GNUC__)
+ [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
+#endif
+ /* INTA# - INTH# */
+ [0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* USB Devs 18/19/22 INTA-C */
+ [0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* SATA */
+ [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x00,0x00,0x1F
+};
+
+static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+#if defined(__GNUC__)
+ [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
+#endif
+ /* INTA# - INTH# */
+ [0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* USB Devs 18/19/20/22 INTA-C */
+ [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* SATA */
+ [0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x00,0x00,0x1F
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device. Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01. This index will define
+ * the interrupt that it should use. Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
+ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
+ {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
+ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
+ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
+ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
+ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
+ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ pirq_data_ptr = mainboard_pirq_data;
+ pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
+/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
+ * once configuration file format for SPI flash storage is complete.
+ */
+#define SIO_PORT 0x2e
+
+static void config_gpio_mux(void)
+{
+ struct device *uart, *gpio;
+
+ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
+ gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
+ if (uart)
+ uart->enabled = CONFIG_APU2_PINMUX_UART_C;
+ if (gpio)
+ gpio->enabled = CONFIG_APU2_PINMUX_GPIO0;
+
+ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
+ gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
+ if (uart)
+ uart->enabled = CONFIG_APU2_PINMUX_UART_D;
+ if (gpio)
+ gpio->enabled = CONFIG_APU2_PINMUX_GPIO1;
+}
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ config_gpio_mux();
+
+ //
+ // Enable the RTC output
+ //
+ pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));
+
+ //
+ // Enable power on from WAKE#
+ //
+ pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
+
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3earlyrestore();
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
new file mode 100644
index 0000000000..896e6373a7
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+#if 0
+u8 picr_data[FCH_INT_TABLE_SIZE] = {
+ 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+u8 intr_data[FCH_INT_TABLE_SIZE] = {
+ 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+
+#endif
+
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+
+ /* Intialize the MP_Table */
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ /*
+ * Type 0: Processor Entries:
+ * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
+ * CPU Signature (Stepping, Model, Family),
+ * Feature Flags
+ */
+ smp_write_processors(mc);
+
+ /*
+ * Type 1: Bus Entries:
+ * Bus ID, Bus Type
+ */
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /*
+ * Type 2: I/O APICs:
+ * APIC ID, Version, APIC Flags:EN, Address
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ /*
+ * Type 3: I/O Interrupt Table Entries:
+ * Int Type, Int Polarity, Int Level, Source Bus ID,
+ * Source Bus IRQ, Dest APIC ID, Dest PIN#
+ */
+
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+
+ /* SMBUS / ACPI */
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
+
+ /* SD card */
+ PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
+
+ /* SATA */
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
+
+ /* on board NIC & Slot PCIE */
+ PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
+ PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
+
+
+ /* GPP0 */
+ PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
+ /* GPP1 */
+ PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
+ /* GPP2 */
+ PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
+ /* GPP3 */
+ PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
+ /* GPP4 */
+ PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
+
+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
new file mode 100644
index 0000000000..f8ed63cd20
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <commonlib/loglevel.h>
+#include <cpu/amd/car.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <Fch/Fch.h>
+#include "gpio_ftns.h"
+
+static void early_lpc_init(void);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ amd_initmmio();
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ early_lpc_init();
+
+ hudson_clk_output_48Mhz();
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
+
+ post_code(0x39);
+ AGESAWRAPPER(amdinitearly);
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ outb(0xEA, 0xCD6);
+ outb(0x1, 0xcd7);
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
+
+
+static void early_lpc_init(void)
+{
+ u32 setting = 0x0;
+
+ //
+ // Configure output disabled, value low, pull up/down disabled
+ //
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
+ //
+ // Configure output enabled, value low, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
+ //
+ // Configure output enabled, value high, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
+}
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 29809f1aec..553add9f5d 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -25,12 +25,12 @@
#include <cbmem.h>
#include "hudson.h"
#include "pci_devs.h"
+#include <Fch/Fch.h>
#if IS_ENABLED(CONFIG_HUDSON_UART)
#include <cpu/x86/msr.h>
#include <delay.h>
-#include <Fch/Fch.h>
void configure_hudson_uart(void)
{
@@ -174,4 +174,20 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
+void hudson_clk_output_48Mhz(void)
+{
+ u32 data, *memptr;
+
+ /*
+ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
+ * 48Mhz will be on ball AP13 (FT3b package)
+ */
+ memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
+ data = *memptr;
+
+ /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
+ data &= (u32)~(1<<2);
+ *memptr = data;
+}
+
#endif