northbridge/amd/amdfam10: Remove commented code

Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16880
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 3 insertions, 162 deletions

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 2ef22ee4d1..7ba91d7ed1 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -211,14 +211,6 @@
 #define   DTH_TRFC_127_5_1G  2
 #define   DTH_TRFC_195_2G    3
 #define   DTH_TRFC_327_5_4G  4
-#if 0
-//DDR3
-#define   DTH_TRFC_90_512M   1
-#define   DTH_TRFC_110_5_1G  2
-#define   DTH_TRFC_160_2G    3
-#define   DTH_TRFC_300_4G    4
-#define   DTH_TRFC_UNDEFINED_8G   5
-#endif
 #define  DTH_TRFC1_SHIFT   23 /*for Logical DIMM1 */
 #define  DTH_TRFC2_SHIFT   26 /*for Logical DIMM2 */
 #define  DTH_TRFC3_SHIFT   29 /*for Logical DIMM3 */
@@ -353,12 +345,6 @@
 #define   DODCC_ProcOdt_300_OHMS  0
 #define   DODCC_ProcOdt_150_OHMS 1
 #define   DODCC_ProcOdt_75_OHMS  2
-#if 0
-//DDR3
-#define   DODCC_ProcOdt_240_OHMS  0
-#define   DODCC_ProcOdt_120_OHMS 1
-#define   DODCC_ProcOdt_60_OHMS  2
-#endif
 
 /*
    for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs
@@ -527,66 +513,6 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 
 /* 04.06.2006 19:12 */
 
-#if 0
-//DDR3
-#define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A
-#define  DDWTC_WrDqsFineDlyByte0_SHIFT 0
-#define   DDWTC_WrDqsFineDlyByte0_MASK 0x1f
-#define  DDWTC_WrDqsGrossDlyByte0_SHIFT 5
-#define   DDWTC_WrDqsGrossDlyByte0_MASK 0x3
-#define  DDWTC_WrDqsFineDlyByte1_SHIFT 8
-#define  DDWTC_WrDqsGrossDlyByte1_SHIFT 13
-#define  DDWTC_WrDqsFineDlyByte2_SHIFT 16
-#define  DDWTC_WrDqsGrossDlyByte2_SHIFT 21
-#define  DDWTC_WrDqsFineDlyByte3_SHIFT 24
-#define  DDWTC_WrDqsGrossDlyByte3_SHIFT 29
-
-#define DRAM_DQS_WRTIE_TIME_CTRL_0_1 0x31 //DIMM0 Channel A
-#define  DDWTC_WrDqsFineDlyByte4_SHIFT 0
-#define  DDWTC_WrDqsGrossDlyByte4_SHIFT 5
-#define  DDWTC_WrDqsFineDlyByte5_SHIFT 8
-#define  DDWTC_WrDqsGrossDlyByte5_SHIFT 13
-#define  DDWTC_WrDqsFineDlyByte6_SHIFT 16
-#define  DDWTC_WrDqsGrossDlyByte6_SHIFT 21
-#define  DDWTC_WrDqsFineDlyByte7_SHIFT 24
-#define  DDWTC_WrDqsGrossDlyByte7_SHIFT 29
-
-#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_0 0x32
-#define  DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0
-#define  DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5
-
-#define DRAM_DQS_WRITE_TIME_CTRL_0_2 0x40 //DIMM0 Channel B
-#define  DDWTC_WrDqsFineDlyByte8_SHIFT 0
-#define  DDWTC_WrDqsGrossDlyByte8_SHIFT 5
-#define  DDWTC_WrDqsFineDlyByte9_SHIFT 8
-#define  DDWTC_WrDqsGrossDlyByte9_SHIFT 13
-#define  DDWTC_WrDqsFineDlyByte10_SHIFT 16
-#define  DDWTC_WrDqsGrossDlyByte10_SHIFT 21
-#define  DDWTC_WrDqsFineDlyByte11_SHIFT 24
-#define  DDWTC_WrDqsGrossDlyByte11_SHIFT 29
-
-#define DRAM_DQS_WRTIE_TIME_CTRL_0_3 0x41 //DIMM0 Channel B
-#define  DDWTC_WrDqsFineDlyByte12_SHIFT 0
-#define  DDWTC_WrDqsGrossDlyByte12_SHIFT 5
-#define  DDWTC_WrDqsFineDlyByte13_SHIFT 8
-#define  DDWTC_WrDqsGrossDlyByte13_SHIFT 13
-#define  DDWTC_WrDqsFineDlyByte14_SHIFT 16
-#define  DDWTC_WrDqsGrossDlyByte14_SHIFT 21
-#define  DDWTC_WrDqsFineDlyByte15_SHIFT 24
-#define  DDWTC_WrDqsGrossDlyByte15_SHIFT 29
-
-#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_1 0x42
-#define  DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0
-#define  DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5
-
-#define DRAM_DQS_WRITE_TIME_CTRL_1_0 0x33 //DIMM1 Channel A
-#define DRAM_DQS_WRTIE_TIME_CTRL_1_1 0x34 //DIMM1 Channel A
-#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_0 0x35
-#define DRAM_DQS_WRITE_TIME_CTRL_1_2 0x43 //DIMM1 Channel B
-#define DRAM_DQS_WRTIE_TIME_CTRL_1_3 0x44 //DIMM1 Channel B
-#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_1 0x45
-#endif
-
 #define DRAM_PHASE_RECOVERY_CTRL_0 0x50
 #define  DPRC_PhRecFineDlyByte0_SHIFT 0
 #define   DDWTC_PhRecFineDlyByte0_MASK 0x1f
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 327a0e68e3..f9c72668af 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -134,8 +134,6 @@ static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
 {
 	dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
 	dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
-//	dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2
-//	dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3
 }
 
 static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index 11f1589251..08698dc3ed 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -71,12 +71,10 @@ void get_pci1234(void)
 	//here we need to set hcdn
 	//1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
 	//2. so at the same time we need update hsdn with hcdn_reg here
-//	printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
 
 	for (j = 0; j < sysconf.ht_c_num; j++) {
 		u32 dwordx;
 		dwordx = sysconf.ht_c_conf_bus[j];
-//		printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
 		dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
 		if ((dwordx & 0x7fd) == dword) { //SBLINK
 			sysconf.pci1234[0] = dwordx;
diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c
index 9259147625..916111caad 100644
--- a/src/northbridge/amd/amdfam10/ht_config.c
+++ b/src/northbridge/amd/amdfam10/ht_config.c
@@ -202,17 +202,6 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 		pci_write_config32(__f1_dev[i], reg+4, tempreg);
 
 	tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
-#if 0
-	// FIXME: can we use VGA reg instead?
-	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-		printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
-			__func__, dev_path(dev), link);
-		tempreg |= PCI_IO_BASE_VGA_EN;
-	}
-	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
-		tempreg |= PCI_IO_BASE_NO_ISA;
-	}
-#endif
 	for (i = 0; i < sysconf.nodes; i++)
 		pci_write_config32(__f1_dev[i], reg, tempreg);
 }
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 40f57046e8..5634441eb8 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -978,8 +978,6 @@ static void amdfam10_domain_set_resources(device_t dev)
 
 		}
 
-//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
-
 		/* split the region to accommodate pci memory space */
 		if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
 			if (basek <= mmio_basek) {
diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h
index bfc0da0238..c1ef29ecee 100644
--- a/src/northbridge/amd/amdfam10/raminit.h
+++ b/src/northbridge/amd/amdfam10/raminit.h
@@ -16,29 +16,6 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
-#if 0
-#if CONFIG_DIMM_SUPPORT == 0x0110
-//FBDIMM REG
-/* each channel can have 8 fbdimm */
-#define DIMM_SOCKETS 8
-struct mem_controller {
-	u32 node_id;
-	pci_devfn_t f0, f1, f2, f3, f4, f5;
-	/* channelA, channelB belong to DCT0,
-	 * channelC, channelD belong to DCT1
-	 * Each DCT may support one ganged logical FBDIMM ---> 128 bit
-	 *			 or a single unganged channel --->64 bit
-	 * a DCT can not support 2 unganged channels
-	 * two DCTs can not be ganged
-	 */
-	u8 spd_switch_addr;
-	u8 spd_addr[DIMM_SOCKETS*4];
-};
-
-#endif
-#endif
-
-//#if (CONFIG_DIMM_SUPPORT & 0x00ff) == 0x0004
 //DDR2 REG and unbuffered : Socket F 1027 and AM3
 /* every channel have 4 DDR2 DIMM for socket F
  *		       2 for socket M2/M3
@@ -63,7 +40,4 @@ struct mem_controller {
 	u8 spd_addr[DIMM_SOCKETS*2];
 };
 
-//#endif
-
-
 #endif
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 7e71cf787b..3d67bddba4 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -20,7 +20,6 @@
 static void setup_resource_map(const u32 *register_values, u32 max)
 {
 	u32 i;
-//	printk(BIOS_DEBUG, "setting up resource map....");
 
 	for (i = 0; i < max; i += 3) {
 		pci_devfn_t dev;
@@ -34,14 +33,13 @@ static void setup_resource_map(const u32 *register_values, u32 max)
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-//	printk(BIOS_DEBUG, "done.\n");
 }
 
 
 void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
 {
 	u32 i;
-//	printk(BIOS_DEBUG, "setting up resource map offset....");
+
 	for (i = 0; i < max; i += 3) {
 		pci_devfn_t dev;
 		u32 where;
@@ -53,7 +51,6 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
 		reg |= register_values[i+2] + offset_io_base;
 		pci_write_config32(dev, where, reg);
 	}
-//	printk(BIOS_DEBUG, "done.\n");
 }
 
 #define RES_PCI_IO 0x10
@@ -124,9 +121,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
 				printk(BIOS_SPEW, "NOW: %08x\n", reg);
 			}
 			break;
-		} // switch
-
-
+		}
 	}
 
 	if (IS_ENABLED(RES_DEBUG))
@@ -180,46 +175,9 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
 			outl(reg, where);
 			}
 			break;
-		} // switch
-
-
+		}
 	}
 
 	if (IS_ENABLED(RES_DEBUG))
 		printk(BIOS_DEBUG, "done.\n");
 }
-
-#if 0
-static void setup_iob_resource_map(const u32 *register_values, u32 max)
-{
-	u32 i;
-
-	for (i = 0; i < max; i += 3) {
-		u32 where;
-		u32 reg;
-
-		where = register_values[i];
-		reg = inb(where);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		outb(reg, where);
-	}
-}
-
-static void setup_io_resource_map(const u32 *register_values, u32 max)
-{
-	u32 i;
-
-	for (i = 0; i < max; i += 3) {
-		u32 where;
-		u32 reg;
-
-		where = register_values[i];
-		reg = inl(where);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-
-		outl(reg, where);
-	}
-}
-#endif