summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-22 13:33:43 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-22 13:33:43 +0000
commite5b44ab4dc3515151379b41cdacffe6a20e4b63c (patch)
treeae8a18afd4af6192678c67032dd620d6c73b8fd0 /src
parent8afdb1c433bff17fc466de33aeb06f0f6f87e470 (diff)
downloadcoreboot-e5b44ab4dc3515151379b41cdacffe6a20e4b63c.tar.xz
All "unknown xy SPI chip" entries claim to have status UNTESTED for
probe/read/erase/write. That is incorrect. A bit of confusion comes from how the #defines are named. We call them TEST_BAD_*, but the message printed by flashrom says: "This flash part has status NOT WORKING for operations:" Something that is unimplemented is definitely not working. Neither of the chip entries mentioned above has erase or write functions implemented, so erase and write are not working. Since their size is unknown, we can't read them in. That means read is not working as well. Probing is a different matter. If a chip-specific probe function had matched, we wouldn't have to handle the chip with the "unknown xy SPI chip" fallback. I'm tempted to call that "not working" as well, but I'm open to discussion on this point. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
0 files changed, 0 insertions, 0 deletions