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authorkane_chen <kane_chen@pegatron.corp-partner.google.com>2018-08-31 17:38:07 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-06 10:30:39 +0000
commite781856af1d68318c2d876ebb9daa7e68db0ae01 (patch)
tree317fc46c4606792b790e37a6baefb3959e11524a /src
parent013ebbfa58e82fb420226adb4da6ce90c285b00d (diff)
downloadcoreboot-e781856af1d68318c2d876ebb9daa7e68db0ae01.tar.xz
mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 78de3caba8..0e8ce4d042 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -203,6 +203,10 @@ chip soc/intel/skylake
.sda_hold = 36,
},
},
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
}"
# Touchscreen