diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2018-06-07 11:43:24 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-25 08:53:38 +0000 |
| commit | f0c50b0e4ba1722c2eeafd75a4c836d0643c888d (patch) | |
| tree | 2c23691762986f752b217285d3e6716ba117ab17 /src | |
| parent | 510758826df22e85c7ecd2d641693c13d745965f (diff) | |
| download | coreboot-f0c50b0e4ba1722c2eeafd75a4c836d0643c888d.tar.xz | |
mb/google/octopus/variants/baseboard: Update DPTF parameters
This patch updates DPTF parameters for Octopus baseboard.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I1456b7b9ee9e02491c66b0709c710e1a7ec08cc5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl | 14 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 88dfce4144..668becc76f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -42,10 +42,10 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_N_63_32" - # PL1 override 8000 mW: Due to error in the energy calculation for + # PL1 override 12000 mW: Due to error in the energy calculation for # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 8W. - register "tdp_pl1_override_mw" = "8000" + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. register "tdp_pl2_override_mw" = "15000" diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl index 140eb4bfd0..2fafa5283f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -14,8 +14,8 @@ */ /* Below values might change after Thermal Tuning. */ -#define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 99 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Battery" @@ -24,12 +24,12 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 46 -#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_PASSIVE 48 +#define DPTF_TSR1_CRITICAL 90 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 58 +#define DPTF_TSR2_PASSIVE 62 #define DPTF_TSR2_CRITICAL 90 #define DPTF_ENABLE_CHARGER @@ -48,7 +48,7 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Effect on Temp Sensor 2 */ @@ -65,7 +65,7 @@ Name (MPPC, Package () Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 12000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 200 /* StepSize */ |