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authorStefan Reinauer <stepan@coresystems.de>2010-01-16 13:48:20 +0000
committerStefan Reinauer <stepan@openbios.org>2010-01-16 13:48:20 +0000
commitf0ec23028096e9c9c912b947d7382e607502dcf7 (patch)
tree4dc87290afb70b28dbf32188e727f2c6d5e0fade /src
parentba8b21c37638837a2afbb95c056b9ce6c25366bd (diff)
downloadcoreboot-f0ec23028096e9c9c912b947d7382e607502dcf7.tar.xz
Fix stack base for Atom CPUs, the resume mechanism (cbmem etc) expects this.
This unifies the base with Core and Core 2 CPUs. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram_disable.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
index d52bf0b178..939ec42aaf 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
@@ -87,10 +87,10 @@ cpu_reset_x:
}
__asm__ volatile (
- /* set new esp */ /* before _RAMBASE */
- "subl %0, %%ebp\n\t"
- "subl %0, %%esp\n\t"
- ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
+ /* set new esp */
+ "movl %0, %%ebp\n\t"
+ "movl %0, %%esp\n\t"
+ ::"a"( CONFIG_RAMBASE + (1024-64)*1024 )
);
{