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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-20 18:01:41 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-27 16:26:54 +0000 |
| commit | f82aa10d56507fd9c3a5abd279fe73df5533e0e4 (patch) | |
| tree | 1968c756a7ebb64968352a491623d819c7dcface /src | |
| parent | b617211910e9c6ff4e3cd92f022ef052a65559a3 (diff) | |
| download | coreboot-f82aa10d56507fd9c3a5abd279fe73df5533e0e4.tar.xz | |
amd/stoneyridge: Clean up include files in northbridge.h
Add an extra include file to northbridge.c for completeness. cpu/msr.h
is already included in cpu/amd/mtrr.h which allows the file to build
properly.
Remove include files that are no longer required for the file.
Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 7ae252f33c..4d44a49564 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -22,11 +22,10 @@ #include <console/console.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> -#include <lib.h> #include <agesawrapper.h> #include <agesawrapper_call.h> #include <soc/northbridge.h> @@ -35,15 +34,6 @@ #include <stdlib.h> #include <string.h> -/* - * AMD vendorcode files. Place at the end so coreboot defaults and maintained - * and not set by vendorcode - */ -#include <AGESA.h> -#include <FieldAccessors.h> -#include <Porting.h> -#include <Topology.h> - typedef struct dram_base_mask { u32 base; /* [47:27] at [28:8] */ u32 mask; /* [47:27] at [28:8] and enable at bit 0 */ |