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authorRob Barnes <robbarnes@google.com>2020-03-27 01:13:21 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-05-18 07:40:47 +0000
commitf836a234e211266d1feffd5f406a692ac0fba164 (patch)
tree12a9a5eba6c2986ed4d2a2dbd8e1ee9873cccabc /src
parent5dd76fd4cc9028f6fc3ab973dda4719abe54da39 (diff)
downloadcoreboot-f836a234e211266d1feffd5f406a692ac0fba164.tar.xz
util/apcb: Add apcb_edit tool
On the Picasso architecture, the PSP is responsible for setting up DRAM before releasing the x86. The APCB (AGESA PSP Configuration Block) contains multiple SPDs and the GPIO numbers used to select the correct SPD. Since the source to build the APCBs is not public, it can't be built as part of the coreboot build. To work around this problem, we use a template APCB and inject the relevant information. BUG=b:147042464 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
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