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authorStefan Reinauer <reinauer@chromium.org>2012-11-13 14:52:04 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-16 01:13:10 +0100
commitfa2fc339c51649b106bf78703cbc17694abcee23 (patch)
tree2060aa4f53a88cb2dd269a83f3f02e16f45ca00a /src
parent55db955bcdad90c9ebd8b755ae417234d46d731a (diff)
downloadcoreboot-fa2fc339c51649b106bf78703cbc17694abcee23.tar.xz
Drop Kconfig variable BOARD_HAS_HARD_RESET
hard_reset was indeed consolidated and moved into the southbridge code a while ago, but the config variable was still kept alife, with some duplicate code. Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/Kconfig1
-rw-r--r--src/Kconfig.deprecated_options10
-rw-r--r--src/mainboard/intel/eagleheights/Kconfig1
-rw-r--r--src/mainboard/intel/eagleheights/reset.c36
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c2
-rw-r--r--src/mainboard/intel/jarrell/Kconfig1
-rw-r--r--src/mainboard/intel/jarrell/power_reset_check.c10
-rw-r--r--src/mainboard/intel/jarrell/reset.c31
-rw-r--r--src/mainboard/intel/jarrell/romstage.c2
-rw-r--r--src/mainboard/intel/xe7501devkit/Kconfig1
-rw-r--r--src/mainboard/intel/xe7501devkit/reset.c8
-rw-r--r--src/mainboard/supermicro/x6dai_g/Kconfig1
-rw-r--r--src/mainboard/supermicro/x6dai_g/reset.c12
-rw-r--r--src/mainboard/supermicro/x6dai_g/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g/Kconfig1
-rw-r--r--src/mainboard/supermicro/x6dhe_g/reset.c13
-rw-r--r--src/mainboard/supermicro/x6dhe_g/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/Kconfig1
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/reset.c13
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/Kconfig1
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/reset.c13
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/Kconfig1
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/reset.c13
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/romstage.c2
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx.h1
-rw-r--r--src/southbridge/intel/i82801cx/reset.c4
28 files changed, 19 insertions, 168 deletions
diff --git a/src/Kconfig b/src/Kconfig
index b5fcdafa3a..062366f50f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -278,7 +278,6 @@ config ACPI_SSDTX_NUM
config HAVE_HARD_RESET
bool
- default y if BOARD_HAS_HARD_RESET
default n
help
This variable specifies whether a given board has a hard_reset
diff --git a/src/Kconfig.deprecated_options b/src/Kconfig.deprecated_options
index 25d5b289b9..0abe76f2fa 100644
--- a/src/Kconfig.deprecated_options
+++ b/src/Kconfig.deprecated_options
@@ -4,16 +4,6 @@
menu "Deprecated"
-# It might be possible to consolidate hard_reset() to southbridges,
-# given that it (usually) uses its registers.
-# The long term goal would be to eliminate hard_reset() from boards.
-config BOARD_HAS_HARD_RESET
- bool
- default n
- help
- This variable specifies whether a given board has a reset.c
- file containing a hard_reset() function.
-
# Will be removed (alongside with the PS/2 init code) once payloads
# reliably support PS/2 init themselves.
config DRIVERS_PS2_KEYBOARD
diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig
index 4fd49fad10..0b765f920e 100644
--- a/src/mainboard/intel/eagleheights/Kconfig
+++ b/src/mainboard/intel/eagleheights/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
- select BOARD_HAS_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select MMCONF_SUPPORT
diff --git a/src/mainboard/intel/eagleheights/reset.c b/src/mainboard/intel/eagleheights/reset.c
deleted file mode 100644
index 006c746dbb..0000000000
--- a/src/mainboard/intel/eagleheights/reset.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <reset.h>
-#if defined (__PRE_RAM__)
-#include <arch/romcc_io.h>
-#endif
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
- outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 1e906efdcb..95ad59f9d4 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,7 +33,7 @@
#include <cpu/intel/speedstep.h>
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
-#include "reset.c"
+#include "southbridge/intel/i3100/reset.c"
#include "superio/intel/i3100/early_serial.c"
#include "superio/smsc/smscsuperio/early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
index a3c34f44b9..2a62777449 100644
--- a/src/mainboard/intel/jarrell/Kconfig
+++ b/src/mainboard/intel/jarrell/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82801EX
select SUPERIO_NSC_PC87427
select ROMCC
- select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c
index 567d15c10f..0ac526f0ee 100644
--- a/src/mainboard/intel/jarrell/power_reset_check.c
+++ b/src/mainboard/intel/jarrell/power_reset_check.c
@@ -1,3 +1,13 @@
+void full_reset(void)
+{
+ /* Enable power on after power fail... */
+ unsigned byte;
+ byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ byte &= 0xfe;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
+
+ outb(0x0e, 0xcf9);
+}
static void power_down_reset_check(void)
{
diff --git a/src/mainboard/intel/jarrell/reset.c b/src/mainboard/intel/jarrell/reset.c
deleted file mode 100644
index 2ecfa48b8f..0000000000
--- a/src/mainboard/intel/jarrell/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
-
-#ifndef __ROMCC__
-/* Used only board-internally by power_reset_check.c and jarell_fixups.c */
-void full_reset(void);
-#endif
-
-void full_reset(void)
-{
- /* Enable power on after power fail... */
- unsigned byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- byte &= 0xfe;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
-
- outb(0x0e, 0xcf9);
-}
-
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 3eff025968..784e7df3e6 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -12,7 +12,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/i82801ex/reset.c"
#include "power_reset_check.c"
#include "jarrell_fixups.c"
#include "superio/nsc/pc87427/early_init.c"
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
index 3f314a623b..276b1f7b5b 100644
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ b/src/mainboard/intel/xe7501devkit/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82801CX
select SUPERIO_SMSC_LPC47B272
select ROMCC
- select BOARD_HAS_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC
diff --git a/src/mainboard/intel/xe7501devkit/reset.c b/src/mainboard/intel/xe7501devkit/reset.c
deleted file mode 100644
index 106920acbe..0000000000
--- a/src/mainboard/intel/xe7501devkit/reset.c
+++ /dev/null
@@ -1,8 +0,0 @@
-#include <reset.h>
-
-#include "southbridge/intel/i82801cx/i82801cx.h"
-
-void hard_reset(void)
-{
- i82801cx_hard_reset();
-}
diff --git a/src/mainboard/supermicro/x6dai_g/Kconfig b/src/mainboard/supermicro/x6dai_g/Kconfig
index bac1008a1a..90a800cee0 100644
--- a/src/mainboard/supermicro/x6dai_g/Kconfig
+++ b/src/mainboard/supermicro/x6dai_g/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_HARD_RESET
- select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/supermicro/x6dai_g/reset.c b/src/mainboard/supermicro/x6dai_g/reset.c
deleted file mode 100644
index 2f21605e7c..0000000000
--- a/src/mainboard/supermicro/x6dai_g/reset.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <arch/io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 479e24c5ae..dda5817335 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -15,7 +15,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/esb6300/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig
index e8466be8a3..03bb0a8508 100644
--- a/src/mainboard/supermicro/x6dhe_g/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_HARD_RESET
- select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/supermicro/x6dhe_g/reset.c b/src/mainboard/supermicro/x6dhe_g/reset.c
deleted file mode 100644
index 1b1bc68d4b..0000000000
--- a/src/mainboard/supermicro/x6dhe_g/reset.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <arch/io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index f2578e5264..37fd2e43d7 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -15,7 +15,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/esb6300/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig
index 0f03336d83..397087cc36 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_NSC_PC87427
select ROMCC
- select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/supermicro/x6dhe_g2/reset.c b/src/mainboard/supermicro/x6dhe_g2/reset.c
deleted file mode 100644
index 1b1bc68d4b..0000000000
--- a/src/mainboard/supermicro/x6dhe_g2/reset.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <arch/io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index d86d83d36a..c9db699a72 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -13,7 +13,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/i82801ex/reset.c"
#include "superio/nsc/pc87427/early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig
index db9fd957b6..0b25fcdb94 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
select ROMCC
- select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/supermicro/x6dhr_ig/reset.c b/src/mainboard/supermicro/x6dhr_ig/reset.c
deleted file mode 100644
index 1b1bc68d4b..0000000000
--- a/src/mainboard/supermicro/x6dhr_ig/reset.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <arch/io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index e77fe7bad5..55e1ee7c2d 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -13,7 +13,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/i82801ex/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
index 395c18405d..70df01ae34 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
select ROMCC
- select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/supermicro/x6dhr_ig2/reset.c b/src/mainboard/supermicro/x6dhr_ig2/reset.c
deleted file mode 100644
index 1b1bc68d4b..0000000000
--- a/src/mainboard/supermicro/x6dhr_ig2/reset.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <arch/io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 91e96a061b..65bfdb2d5e 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -13,7 +13,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/i82801ex/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h
index 28428830e2..f196fa324f 100644
--- a/src/southbridge/intel/i82801cx/i82801cx.h
+++ b/src/southbridge/intel/i82801cx/i82801cx.h
@@ -4,7 +4,6 @@
#if !defined(__PRE_RAM__)
#include <device/device.h>
void i82801cx_enable(device_t dev);
-void i82801cx_hard_reset(void);
#endif
diff --git a/src/southbridge/intel/i82801cx/reset.c b/src/southbridge/intel/i82801cx/reset.c
index bd479de758..6883ff089b 100644
--- a/src/southbridge/intel/i82801cx/reset.c
+++ b/src/southbridge/intel/i82801cx/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
-#include "i82801cx.h"
+#include <reset.h>
-void i82801cx_hard_reset(void)
+void hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
// Hard reset without power cycle