soc/intel/braswell: add default option to use public FSP

The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.

To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.

Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.

Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

12 files changed, 62 insertions, 51 deletions

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index b3c6790e57..aac14c06c3 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN
 	select HAVE_ACPI_RESUME
 	select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN
 	select SYSTEM_TYPE_LAPTOP
+	select USE_GOOGLE_FSP
 
 if BOARD_GOOGLE_BASEBOARD_CYAN
 
diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb
index 2e708af0d6..a1ab510810 100644
--- a/src/mainboard/google/cyan/variants/celes/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb
@@ -73,12 +73,6 @@ chip soc/intel/braswell
 	register "ISPEnable" = "0"		# Disable IUNIT
 	register "ISPPciDevConfig" = "3"
 	register "PcdSdDetectChk" = "0"		# Disable SD card detect
-	# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-	register "D0Usb2Port0PerPortRXISet" = "2"
-	register "D0Usb2Port1PerPortRXISet" = "2"
-	register "D0Usb2Port2PerPortRXISet" = "2"
-	register "D0Usb2Port3PerPortRXISet" = "2"
-	register "D0Usb2Port4PerPortRXISet" = "2"
 
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c
index 88b17f5da7..6c522a1d0c 100644
--- a/src/mainboard/google/cyan/variants/celes/ramstage.c
+++ b/src/mainboard/google/cyan/variants/celes/ramstage.c
@@ -19,29 +19,36 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 {
 	if (SocStepping() >= SocD0) {
 
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
 		params->Usb2Port0PerPortPeTxiSet = 7;
 		params->Usb2Port0PerPortTxiSet = 0;
 		params->Usb2Port0IUsbTxEmphasisEn = 3;
 		params->Usb2Port0PerPortTxPeHalf = 1;
+		params->D0Usb2Port0PerPortRXISet = 2;
 
 		params->Usb2Port1PerPortPeTxiSet = 7;
 		params->Usb2Port1PerPortTxiSet = 0;
 		params->Usb2Port1IUsbTxEmphasisEn = 3;
 		params->Usb2Port1PerPortTxPeHalf = 1;
+		params->D0Usb2Port1PerPortRXISet = 2;
 
 		params->Usb2Port2PerPortPeTxiSet = 7;
 		params->Usb2Port2PerPortTxiSet = 6;
 		params->Usb2Port2IUsbTxEmphasisEn = 3;
 		params->Usb2Port2PerPortTxPeHalf = 1;
+		params->D0Usb2Port2PerPortRXISet = 2;
 
 		params->Usb2Port3PerPortPeTxiSet = 7;
 		params->Usb2Port3PerPortTxiSet = 6;
 		params->Usb2Port3IUsbTxEmphasisEn = 3;
 		params->Usb2Port3PerPortTxPeHalf = 1;
+		params->D0Usb2Port3PerPortRXISet = 2;
 
 		params->Usb2Port4PerPortPeTxiSet = 7;
 		params->Usb2Port4PerPortTxiSet = 6;
 		params->Usb2Port4IUsbTxEmphasisEn = 3;
 		params->Usb2Port4PerPortTxPeHalf = 1;
+		params->D0Usb2Port4PerPortRXISet = 2;
 	}
 }
diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc
index 5e94e715fa..7799e8d2b3 100644
--- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc
+++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc
@@ -18,6 +18,7 @@ romstage-y += romstage.c
 romstage-y += spd_util.c
 
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
 
 SPD_BIN = $(obj)/spd.bin
 
diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb
index 1ce056f32e..807dbcb2fe 100644
--- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/kefka/devicetree.cb
@@ -80,13 +80,6 @@ chip soc/intel/braswell
 	register "I2C5Frequency" = "1"
 	register "I2C6Frequency" = "1"
 
-        # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-        register "D0Usb2Port0PerPortRXISet" = "2"
-        register "D0Usb2Port1PerPortRXISet" = "2"
-        register "D0Usb2Port2PerPortRXISet" = "2"
-        register "D0Usb2Port3PerPortRXISet" = "2"
-        register "D0Usb2Port4PerPortRXISet" = "2"
-
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c
new file mode 100644
index 0000000000..d790708cce
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+
+void board_silicon_USB2_override(SILICON_INIT_UPD *params)
+{
+	if (SocStepping() >= SocD0) {
+
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
+		params->D0Usb2Port0PerPortRXISet = 2;
+		params->D0Usb2Port1PerPortRXISet = 2;
+		params->D0Usb2Port2PerPortRXISet = 2;
+		params->D0Usb2Port3PerPortRXISet = 2;
+		params->D0Usb2Port4PerPortRXISet = 2;
+	}
+}
diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb
index 65e662c5dd..e1bbb0ac5b 100644
--- a/src/mainboard/google/cyan/variants/relm/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb
@@ -80,13 +80,6 @@ chip soc/intel/braswell
 	register "I2C5Frequency" = "1"
 	register "I2C6Frequency" = "1"
 
-	# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-	register "D0Usb2Port0PerPortRXISet" = "2"
-	register "D0Usb2Port1PerPortRXISet" = "2"
-	register "D0Usb2Port2PerPortRXISet" = "2"
-	register "D0Usb2Port3PerPortRXISet" = "2"
-	register "D0Usb2Port4PerPortRXISet" = "2"
-
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c
index 27f9dfa241..3fbd2aebd9 100644
--- a/src/mainboard/google/cyan/variants/relm/ramstage.c
+++ b/src/mainboard/google/cyan/variants/relm/ramstage.c
@@ -36,5 +36,13 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 		params->Usb2Port3PerPortTxiSet = 0;
 		params->Usb2Port3IUsbTxEmphasisEn = 2;
 		params->Usb2Port3PerPortTxPeHalf = 1;
+
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
+		params->D0Usb2Port0PerPortRXISet = 2;
+		params->D0Usb2Port1PerPortRXISet = 2;
+		params->D0Usb2Port2PerPortRXISet = 2;
+		params->D0Usb2Port3PerPortRXISet = 2;
+		params->D0Usb2Port4PerPortRXISet = 2;
 	}
 }
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index a0c07084b8..ed5c9728a3 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -135,4 +135,18 @@ config DISABLE_HPET
 	 Enable this to disable the HPET support
 	 Solves the Linux MP-BIOS bug timer not connected.
 
+config USE_GOOGLE_FSP
+	bool
+	help
+	 Select this to use Google's custom Braswell FSP header/binary
+	 instead of the public release on Github. Only google/cyan
+	 variants require this; all other boards should use the public release.
+
+config FSP_HEADER_PATH
+	string
+	default "$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP
+	default "3rdparty/fsp/BraswellFspBinPkg/Include/"
+	help
+	 Location of FSP header file FspUpdVpd.h
+
 endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index a538f7daff..a7ed4c5388 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -56,7 +56,7 @@ smm-y += tsc_freq.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell
+CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH))
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
 
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 4be13cdea3..900b2f33fd 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -129,36 +129,26 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
 	params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn;
 	params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf;
-	if (config->D0Usb2Port0PerPortRXISet != 0)
-		params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet;
 
 	params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet;
 	params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet;
 	params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn;
 	params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf;
-	if (config->D0Usb2Port1PerPortRXISet != 0)
-		params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet;
 
 	params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet;
 	params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet;
 	params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn;
 	params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf;
-	if (config->D0Usb2Port2PerPortRXISet != 0)
-		params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet;
 
 	params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet;
 	params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet;
 	params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn;
 	params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf;
-	if (config->D0Usb2Port3PerPortRXISet != 0)
-		params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet;
 
 	params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet;
 	params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet;
 	params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn;
 	params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf;
-	if (config->D0Usb2Port4PerPortRXISet != 0)
-		params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet;
 
 	params->Usb3Lane0Ow2tapgen2deemph3p5 =
 		config->Usb3Lane0Ow2tapgen2deemph3p5;
@@ -266,9 +256,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1,
 		old->Usb2Port0PerPortTxPeHalf,
 		new->Usb2Port0PerPortTxPeHalf);
-	fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1,
-		old->D0Usb2Port0PerPortRXISet,
-		new->D0Usb2Port0PerPortRXISet);
 	fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1,
 		old->Usb2Port1PerPortPeTxiSet,
 		new->Usb2Port1PerPortPeTxiSet);
@@ -281,9 +268,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1,
 		old->Usb2Port1PerPortTxPeHalf,
 		new->Usb2Port1PerPortTxPeHalf);
-	fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1,
-		old->D0Usb2Port1PerPortRXISet,
-		new->D0Usb2Port1PerPortRXISet);
 	fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1,
 		old->Usb2Port2PerPortPeTxiSet,
 		new->Usb2Port2PerPortPeTxiSet);
@@ -296,9 +280,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1,
 		old->Usb2Port2PerPortTxPeHalf,
 		new->Usb2Port2PerPortTxPeHalf);
-	fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1,
-		old->D0Usb2Port2PerPortRXISet,
-		new->D0Usb2Port2PerPortRXISet);
 	fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1,
 		old->Usb2Port3PerPortPeTxiSet,
 		new->Usb2Port3PerPortPeTxiSet);
@@ -311,9 +292,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1,
 		old->Usb2Port3PerPortTxPeHalf,
 		new->Usb2Port3PerPortTxPeHalf);
-	fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1,
-		old->D0Usb2Port3PerPortRXISet,
-		new->D0Usb2Port3PerPortRXISet);
 	fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1,
 		old->Usb2Port4PerPortPeTxiSet,
 		new->Usb2Port4PerPortPeTxiSet);
@@ -326,9 +304,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1,
 		old->Usb2Port4PerPortTxPeHalf,
 		new->Usb2Port4PerPortTxPeHalf);
-	fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1,
-		old->D0Usb2Port4PerPortRXISet,
-		new->D0Usb2Port4PerPortRXISet);
 	fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1,
 		old->Usb3Lane0Ow2tapgen2deemph3p5,
 		new->Usb3Lane0Ow2tapgen2deemph3p5);
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 4afaf44417..bb06dd595a 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -172,11 +172,6 @@ struct soc_intel_braswell_config {
 	UINT8  I2C4Frequency;
 	UINT8  I2C5Frequency;
 	UINT8  I2C6Frequency;
-	UINT8  D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/
-	UINT8  D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/
-	UINT8  D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/
-	UINT8  D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/
-	UINT8  D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/
 };
 
 extern struct chip_operations soc_intel_braswell_ops;