diff options
| author | David Hendricks <dhendrix@chromium.org> | 2015-09-25 15:21:35 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-25 07:31:57 +0100 |
| commit | fd9cdf6dec65aa4d6fd36cc6983c2f24f83c623e (patch) | |
| tree | 0b071ce6ef1007c11c082dc1f6d4958299946a96 /src | |
| parent | 4a14dc2fd9e1f6de017f3eb436d74702078a106c (diff) | |
| download | coreboot-fd9cdf6dec65aa4d6fd36cc6983c2f24f83c623e.tar.xz | |
google/veyron_rialto: Throttle to 1416MHz @ 1200mV in bootblock
The 1392MHz value used to throttle the RK3288 earlier was somewhat
arbitrary. This patch brings the throttling in sync with the operating
points specified in the Linux device tree for RK3288.
BUG=chrome-os-partner:42054
BRANCH=none
TEST=Saw print statement in image.serial.bin indicating that APLL
was set to the desired frequency.
Change-Id: Ibe570267bbfe23f010ad5e1ea651356291b9c63c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a146f23b13cb0f6da93ada65648cf33ecfaaa7d6
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I6bcdb5fd6ffa3f9a22e79c519bdb7980492e2318
Original-Reviewed-on: https://chromium-review.googlesource.com/302633
Reviewed-on: http://review.coreboot.org/12137
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/veyron_rialto/bootblock.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index a539c08ba8..e87d8d17e2 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -63,9 +63,7 @@ void bootblock_mainboard_init(void) /* Slowly raise to max CPU voltage to prevent overshoot */ rk808_configure_buck(1, 1200); udelay(175);/* Must wait for voltage to stabilize,2mV/us */ - rk808_configure_buck(1, 1400); - udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(APLL_1392_MHZ); + rkclk_configure_cpu(APLL_1416_MHZ); /* i2c1 for tpm */ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); |