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authorDuncan Laurie <dlaurie@chromium.org>2013-05-10 11:00:56 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 06:20:37 +0100
commitffa0fa4660c8c9e605773ce9ad21d5bef209613d (patch)
treeda3051fcdabf62f1070b9d5b4c7eb6627e6be4df /src
parent4d019c9ee2d5d25cc8eac2b97586f761b79e49b2 (diff)
downloadcoreboot-ffa0fa4660c8c9e605773ce9ad21d5bef209613d.tar.xz
slippy: Add EC to the device tree
This lets the keyboard init get called properly. Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4167 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/slippy/devicetree.cb10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 5fb3cb4c1b..665e6dcecc 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -84,7 +84,15 @@ chip northbridge/intel/haswell
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on end # LPC bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal