boot to kernel

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 64 insertions, 176 deletions

diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index 51fbe2ae87..f2802b67ca 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -169,7 +169,7 @@ cpuRegInit (void){
 /* */
 /*  FooGlue Setup*/
 /* */
-#if 0
+#if 1
 	/*  Enable CIS mode B in FooGlue*/
 	msrnum = MSR_FG + 0x10;
 	msr = rdmsr(msrnum);
diff --git a/src/cpu/amd/model_gx2/model_gx2_init.c b/src/cpu/amd/model_gx2/model_gx2_init.c
index 9fc5d2679d..c6ad683ff8 100644
--- a/src/cpu/amd/model_gx2/model_gx2_init.c
+++ b/src/cpu/amd/model_gx2/model_gx2_init.c
@@ -6,88 +6,29 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
 
-#if 0
-#include <cpu/amd/gx2def.h>
-#include <arch/io.h>
 
-static void gx2_cpu_setup(void)
+static void vsm_end_post_smi(void)
 {
-	unsigned char rreg;
-	unsigned char cpu_table[] = {
-		0xc1, 0x00,		/* NO SMIs */
-		0xc3, 0x14,		/* Enable CPU config register */
-		0x20, 0x00,		/* */
-		0xb8, GX_BASE>>30,	/* Enable GXBASE address */
-		0xc2, 0x00,
-		0xe8, 0x98,
-		0xc3, 0xf8,		/* Enable CPU config register */
-		0x00, 0x00
-		};
-	unsigned char *cPtr = cpu_table;
-
-	while(rreg = *cPtr++) {
-		unsigned char rval = *cPtr++;
-		outb(rreg, 0x22);
-		outb(rval, 0x23);
-		}
-
-	outb(0xff, 0x22);		/* DIR1 -- Identification register 1 */
-	if(inb(0x23) > 0x63) {		/* Rev greater than R3 */
-		outb(0xe8, 0x22);
-		outb(inb(0x23) | 0x20, 0x23);	/* Enable FPU Fast Mode */
-
-		outb(0xf0, 0x22);
-		outb(inb(0x23) | 0x02, 0x23);	/* Incrementor on */
-
-		outb(0x20, 0x22);
-		outb(inb(0x23) | 0x24, 0x23);	/* Bit 5 must be on */
-						/* Bit 2 Incrementor margin 10 */
-
-	}
-}
-
-static void gx2_gx_setup(void)
-{
-unsigned long gx_setup_table[] = {
-	GX_BASE + DC_UNLOCK, 		DC_UNLOCK_MAGIC,
-	GX_BASE + DC_GENERAL_CFG, 		0,
-	GX_BASE + DC_UNLOCK, 		0,
-	GX_BASE + BC_DRAM_TOP, 		0x3fffffff,
-	GX_BASE + BC_XMAP_1, 		0x60,
-	GX_BASE + BC_XMAP_2, 		0,
-	GX_BASE + BC_XMAP_3, 		0,
-	GX_BASE + MC_BANK_CFG, 		0x00700070,
-	GX_BASE + MC_MEM_CNTRL1, 	XBUSARB,
-	GX_BASE + MC_GBASE_ADD, 	0xff,
-	0, 				0
-	};
-
-unsigned long *gxPtr = gx_setup_table;
-unsigned long *gxdPtr;
-unsigned long addr;
-
-	while(addr = *gxPtr++) {
-		gxdPtr = (unsigned long *)addr;
-		*gxdPtr = *gxPtr++;
-	}
+	__asm__ volatile (
+			  "push %ax\n"
+			  "mov $0x5000, %ax\n"
+			  ".byte 0x0f, 0x38\n"
+			  "pop %ax\n"
+			  );
 }
-#endif
 
 static void model_gx2_init(device_t dev)
 {
-	void do_vsmbios(void);
-#if 0
-	gx2_cpu_setup();
-	gx2_gx_setup();
-#endif
 	printk_debug("model_gx2_init\n");
+
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
 	/* Enable the local cpu apics */
-	setup_lapic();
+	//setup_lapic();
+
+	vsm_end_post_smi();
 
-	do_vsmbios();
 	printk_debug("model_gx2_init DONE\n");
 };
 
@@ -96,7 +37,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_CYRIX, 0x0540 },
+	{ X86_VENDOR_NSC, 0x0552 },
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index b462fcd8fd..3f65774f66 100644
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -283,6 +283,10 @@ void do_vsmbios(void)
 	/* ecx gets smm, edx gets sysm */
 	printk_err("Call real_mode_switch_call_vsm\n");
 	real_mode_switch_call_vsm(0x10000026, 0x10000028);
+
+	/* restart timer 1 */
+	outb(0x56, 0x43);
+	outb(0x12, 0x41);
 }
 
 
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index c3771c2c6f..481d5ef1bf 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -448,6 +448,15 @@
 #define PCI_DEVICE_ID_AMD_8132_PCIX     0x7458
 #define PCI_DEVICE_ID_AMD_8132_IOAPIC   0x7459
 
+#define PCI_DEVICE_ID_AMD_CS5536_ISA	0x2090
+#define PCI_DEVICE_ID_AMD_CS5536_FLASH	0x2091
+#define PCI_DEVICE_ID_AMD_CS5536_IDE	0x2092
+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO	0x2093
+#define PCI_DEVICE_ID_AMD_CS5536_OHCI	0x2094
+#define PCI_DEVICE_ID_AMD_CS5536_EHCI	0x2095
+#define PCI_DEVICE_ID_AMD_CS5536_UDC	0x2096
+#define PCI_DEVICE_ID_AMD_CS5536_OTG	0x2097
+
 #define PCI_VENDOR_ID_TRIDENT		0x1023
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb
index f08593143f..a7962f51d0 100644
--- a/src/mainboard/amd/rumba/Config.lb
+++ b/src/mainboard/amd/rumba/Config.lb
@@ -124,20 +124,22 @@ dir /pc80
 config chip.h
 
 chip northbridge/amd/gx2
-  device pci_domain 0 on 
-    device pci 0.0 on end
-      chip southbridge/amd/cs5535
-        device pci 12.0 on
-        device pci 12.1 off end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 off end 	# Audio
-        device pci 12.4 off end		# VGA
-      end
-    end
-  end
-
-  chip cpu/amd/model_gx2
-  end
-
+	device apic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device apic 0 on end
+		end
+	end
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+        		device pci d.0 on end	# Realtek 8139 LAN
+        		device pci f.0 on end	# ISA Bridge
+        		device pci f.2 on end	# IDE Controller
+        		device pci f.3 on end 	# Audio
+        		device pci f.4 on end	# OHCI
+			device pci f.4 on end	# UHCI
+      		end
+    	end
 end
 
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 3f966047ca..7dca7fc55d 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -108,39 +108,14 @@ static void msr_init(void)
 
 	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-        //__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
-        //__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
-        //__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
-        //__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
-
-	// __builtin_wrmsr(0x10000080, 0x3, 0x0);
 
         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-	//__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
-        //__builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
-        //__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
-        //__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
-
-        //__builtin_wrmsr(0x50002001, 0x27, 0x0);
-        //__builtin_wrmsr(0x4c002001, 0x1, 0x0);
-#if 1
-        //__builtin_wrmsr(0x4c00000c, 0x0, 0x08);
-	//__builtin_wrmsr(0x4c000016, 0x0, 0x0);
-	//__builtin_wrmsr(0x4c00000c, 0x1, 0x0);
-	//__builtin_wrmsr(0x4c00005e, 0x03880000, 0x00);
-	//__builtin_wrmsr(0x4c00006f, 0x0000f000, 0x00);
-	//__builtin_wrmsr(0x4c00005f, 0x08000000, 0x00);
-	//__builtin_wrmsr(0x4c00000d, 0x82b5ad68, 0x80ad6b57);
-	//__builtin_wrmsr(0x4c00000c, 0x0, 0x0);
-#endif
 }
 
 
 static void main(unsigned long bist)
 {
-	msr_t msr;
 	static const struct mem_controller memctrl [] = {
 		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
 	};
@@ -152,7 +127,7 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 
-	cs5535_early_setup();
+	cs5536_early_setup();
 
 	pll_reset();
 
@@ -161,10 +136,6 @@ static void main(unsigned long bist)
 	
 	sdram_initialize(1, memctrl);
 
-	print_err("reading MSR 0x51102000\n\t");
-	msr = rdmsr(0x51102000);
-	print_debug_hex32(msr.hi);
-
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index f08593143f..a7962f51d0 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -124,20 +124,22 @@ dir /pc80
 config chip.h
 
 chip northbridge/amd/gx2
-  device pci_domain 0 on 
-    device pci 0.0 on end
-      chip southbridge/amd/cs5535
-        device pci 12.0 on
-        device pci 12.1 off end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 off end 	# Audio
-        device pci 12.4 off end		# VGA
-      end
-    end
-  end
-
-  chip cpu/amd/model_gx2
-  end
-
+	device apic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device apic 0 on end
+		end
+	end
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+        		device pci d.0 on end	# Realtek 8139 LAN
+        		device pci f.0 on end	# ISA Bridge
+        		device pci f.2 on end	# IDE Controller
+        		device pci f.3 on end 	# Audio
+        		device pci f.4 on end	# OHCI
+			device pci f.4 on end	# UHCI
+      		end
+    	end
 end
 
diff --git a/src/mainboard/olpc/rev_a/auto.c b/src/mainboard/olpc/rev_a/auto.c
index 17ded0dc97..a5716783ef 100644
--- a/src/mainboard/olpc/rev_a/auto.c
+++ b/src/mainboard/olpc/rev_a/auto.c
@@ -138,33 +138,9 @@ static void msr_init(void)
 
 	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-        __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
-        __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
-        __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
-        __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
-
-        __builtin_wrmsr(0x10000080, 0x3, 0x0);
 
         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-	__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
-        __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
-        __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
-        __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
-
-        __builtin_wrmsr(0x50002001, 0x27, 0x0);
-        __builtin_wrmsr(0x4c002001, 0x1, 0x0);
-#if 1
-        __builtin_wrmsr(0x4c00000c, 0x0, 0x08);
-	__builtin_wrmsr(0x4c000016, 0x0, 0x0);
-	__builtin_wrmsr(0x4c00000c, 0x1, 0x0);
-	__builtin_wrmsr(0x4c00005e, 0x03880000, 0x00);
-	__builtin_wrmsr(0x4c00006f, 0x0000f000, 0x00);
-	__builtin_wrmsr(0x4c00005f, 0x08000000, 0x00);
-	__builtin_wrmsr(0x4c00000d, 0x82b5ad68, 0x80ad6b57);
-	__builtin_wrmsr(0x4c00000c, 0x0, 0x0);
-#endif
 }
 
 	
@@ -181,7 +157,7 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 
-	cs5535_early_setup();
+	cs5536_early_setup();
 
 	pll_reset();
 
@@ -189,7 +165,6 @@ static void main(unsigned long bist)
 	print_err("done cpuRegInit\n");
 	
 	sdram_initialize(1, memctrl);
-
 	
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 809a440e77..1dd4c9c7a3 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -237,17 +237,6 @@ setup_gx2(void)
 	}
 }
 
-
-static void optimize_xbus(device_t dev)
-{
-	/* Optimise X-Bus performance */
-/*	pci_write_config8(dev, 0x40, 0x1e);
-	pci_write_config8(dev, 0x41, 0x52);
-	pci_write_config8(dev, 0x43, 0xc1);
-	pci_write_config8(dev, 0x44, 0x00);
-*/
-}
-
 static void enable_shadow(device_t dev)
 {
 	
@@ -257,11 +246,9 @@ static void northbridge_init(device_t dev)
 {
 	printk_debug("northbridge: %s()\n", __FUNCTION__);
 	
-	optimize_xbus(dev);
 	enable_shadow(dev);
 }
 
-
 static struct device_operations northbridge_operations = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
@@ -273,12 +260,10 @@ static struct device_operations northbridge_operations = {
 
 static struct pci_driver northbridge_driver __pci_driver = {
 	.ops = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_CYRIX,
-	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_GX2,
 };
 
-
-
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
 static void pci_domain_read_resources(device_t dev)
@@ -441,7 +426,6 @@ static void enable_dev(struct device *dev)
 		pci_set_method(dev);
 		ram_resource(dev, 0, 0, (sizeram() - RAMADJUSTMB)*1024);
         } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-
 		printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         }