google/edgar: add new board as variant of cyan baseboard

Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.

- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
  variants other than cyan

Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data

Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

19 files changed, 865 insertions, 7 deletions

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index f4f98309d6..b375729849 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -11,6 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN
 	select MAINBOARD_HAS_LPC_TPM
 	select SOC_INTEL_BRASWELL
 	select HAVE_ACPI_RESUME
+	select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN
 
 if BOARD_GOOGLE_BASEBOARD_CYAN
 
@@ -33,13 +34,20 @@ config MAINBOARD_DIR
 	string
 	default google/cyan
 
+config MAINBOARD_FAMILY
+	string
+	default "Intel_Strago" if !BOARD_GOOGLE_CYAN
+	default ""
+
 config VARIANT_DIR
 	string
 	default "cyan" if BOARD_GOOGLE_CYAN
+	default "edgar" if BOARD_GOOGLE_EDGAR
 
 config MAINBOARD_PART_NUMBER
 	string
 	default "Cyan" if BOARD_GOOGLE_CYAN
+	default "Edgar" if BOARD_GOOGLE_EDGAR
 
 config MAINBOARD_VENDOR
 	string
@@ -48,6 +56,7 @@ config MAINBOARD_VENDOR
 config DEVICETREE
 	string
 	default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN
+	default "variants/edgar/devicetree.cb" if BOARD_GOOGLE_EDGAR
 
 config VGA_BIOS_FILE
 	string
@@ -70,5 +79,6 @@ config GBB_HWID
 	string
 	depends on CHROMEOS
 	default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN
+	default "EDGAR TEST A-A 2507" if BOARD_GOOGLE_EDGAR
 
 endif # BOARD_GOOGLE_BASEBOARD_CYAN
diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name
index 91e10c9613..50f9c581c6 100644
--- a/src/mainboard/google/cyan/Kconfig.name
+++ b/src/mainboard/google/cyan/Kconfig.name
@@ -1,3 +1,7 @@
 config BOARD_GOOGLE_CYAN
 	bool "Cyan"
 	select BOARD_GOOGLE_BASEBOARD_CYAN
+
+config BOARD_GOOGLE_EDGAR
+	bool "Edgar"
+	select BOARD_GOOGLE_BASEBOARD_CYAN
diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl
new file mode 100644
index 0000000000..d3fa84eaa7
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C5)
+{
+	/* Realtek Audio Codec */
+	Device (RTEK)   /* Audio Codec driver I2C */
+	{
+		Name (_ADR, 0)
+		Name (_HID, AUDIO_CODEC_HID)
+		Name (_CID, AUDIO_CODEC_CID)
+		Name (_DDN, AUDIO_CODEC_DDN)
+		Name (_UID, 1)
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(SBUF,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					AUDIO_CODEC_I2C_ADDR,	/* SlaveAddress: bus address */
+					ControllerInitiated,	/* SlaveMode: default to ControllerInitiated */
+					400000,			/* ConnectionSpeed: in Hz */
+					AddressingMode7Bit,	/* Addressing Mode: default to 7 bit */
+					"\\_SB.PCI0.I2C5",	/* ResourceSource: I2C bus controller name */
+				)
+
+			 /* Jack Detect (index 0) */
+			 GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+				  "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX }
+			} )
+			Return (SBUF)
+		}
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
+
+Scope (\_SB.PCI0.LPEA)
+{
+	Name (GBUF, ResourceTemplate ()
+	{
+		/* Jack Detect (index 0) */
+		GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+			 "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX }
+	})
+}
diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c
index a0da53f52c..e7c91d2080 100644
--- a/src/mainboard/google/cyan/acpi_tables.c
+++ b/src/mainboard/google/cyan/acpi_tables.c
@@ -33,6 +33,10 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 
 	/* Enable DPTF */
 	gnvs->dpte = 1;
+
+	/* Disable PMIC I2C port for ACPI for all boards except cyan */
+	if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN))
+		gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
index 8aac84f57f..78856429d2 100644
--- a/src/mainboard/google/cyan/chromeos.c
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <rules.h>
+#include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -24,6 +25,8 @@
 #define WP_STATUS_PAD_CFG0	0x4838
 #define WP_STATUS_PAD_CFG1	0x483C
 
+#define WP_GPIO			GP_E_22
+
 #if ENV_RAMSTAGE
 #include <boot/coreboot_tables.h>
 
@@ -52,15 +55,23 @@ int get_write_protect_state(void)
 	 * in the reading.
 	 */
 #if ENV_ROMSTAGE
-	write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0),
-	(PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
-	write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1),
-		PAD_CONFIG1_DEFAULT0);
+	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+		write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0),
+			(PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
+		write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1),
+			PAD_CONFIG1_DEFAULT0);
+	} else {
+		gpio_input_pullup(WP_GPIO);
+	}
 #endif
 
 	/* WP is enabled when the pin is reading high. */
-	return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
-		& PAD_VAL_HIGH);
+	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+		return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
+			& PAD_VAL_HIGH);
+	} else {
+		return !!gpio_get(WP_GPIO);
+	}
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
index 28a8a46a39..57c40e09bd 100644
--- a/src/mainboard/google/cyan/romstage.c
+++ b/src/mainboard/google/cyan/romstage.c
@@ -15,6 +15,7 @@
  */
 
 #include <soc/romstage.h>
+#include <chip.h>
 
 /* All FSP specific code goes in this block */
 void mainboard_romstage_entry(struct romstage_params *rp)
@@ -32,6 +33,9 @@ void mainboard_memory_init_params(struct romstage_params *params,
 	MEMORY_INIT_UPD *memory_params)
 {
 	/* Update SPD data */
+	if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+		memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
+	}
 	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
 	memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
 	memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c
index 75c1890d2c..b09fea321e 100644
--- a/src/mainboard/google/cyan/smihandler.c
+++ b/src/mainboard/google/cyan/smihandler.c
@@ -152,6 +152,11 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 	/* Clear pending events that may trigger immediate wake */
 	while (google_chromeec_get_event() != 0)
 		;
+
+	/* Set LPC lines to low power in S3/S5. */
+	if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) {
+		lpc_set_low_power();
+	}
 #endif
 }
 
diff --git a/src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex b/src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex
new file mode 100644
index 0000000000..a8e0c26d61
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
+48 39 43 43 4E 4E 4E 38 4A 54 42 4C 41 52 2D 4E
+55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
new file mode 100644
index 0000000000..056dc258be
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
@@ -0,0 +1,32 @@
+91 20 F1 03 04 11 05 0B
+03 11 01 08 0A 00 40 01
+78 78 90 50 90 11 50 E0
+10 04 3C 3C 01 90 00 00
+00 00 00 00 00 00 00 A8
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01
+00 00 55 00 00 00 00 00
+4B 34 45 38 45 33 30 34
+45 45 2D 45 47 43 45 20
+20 20 00 00 80 CE 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
new file mode 100644
index 0000000000..6d9ae526b2
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
@@ -0,0 +1,32 @@
+91 20 F1 03 05 19 05 03
+03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0
+90 06 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01
+00 00 55 00 00 00 00 00
+4B 34 45 38 45 33 32 34
+45 42 2D 45 47 43 46 20
+20 20 00 00 80 CE 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index f38fc58ff8..a3db2ed6f4 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -137,7 +137,11 @@ static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm)
 	}
 
 	/* Parse the SPD data to determine the DIMM information */
-	dimm->ddr_type = MEMORY_DEVICE_DDR3;
+	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+		dimm->ddr_type = MEMORY_DEVICE_DDR3;
+	} else {
+		dimm->ddr_type = MEMORY_DEVICE_LPDDR3;
+	}
 	dimm->dimm_size = capmb / 8 * busw / devw * ranks;  /* MiB */
 	dimm->mod_type = spd[3] & 0xf;
 	memcpy((char *)&dimm->module_part_number[0], &spd[0x80],
diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc
new file mode 100644
index 0000000000..e553c885d9
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc
@@ -0,0 +1,43 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+ramstage-y += gpio.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES =  samsung_dimm_K4E8E304EE-EGCE
+SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD
+SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCE
+SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF
+SPD_SOURCES += empty
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/cyan/variants/edgar/board_info.txt b/src/mainboard/google/cyan/variants/edgar/board_info.txt
new file mode 100644
index 0000000000..e50ba0b192
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Edgar
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/cyan/variants/edgar/devicetree.cb b/src/mainboard/google/cyan/variants/edgar/devicetree.cb
new file mode 100644
index 0000000000..2033f9e4e8
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/devicetree.cb
@@ -0,0 +1,144 @@
+chip soc/intel/braswell
+
+	############################################################
+	# Set the parameters for MemoryInit
+	############################################################
+
+	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
+
+	register "PcdMrcInitMmioSize" = "0x0800"
+	register "PcdMrcInitSpdAddr1" = "0xa0"
+	register "PcdMrcInitSpdAddr2" = "0xa2"
+	register "PcdIgdDvmt50PreAlloc" = "1"
+	register "PcdApertureSize" = "2"
+	register "PcdGttSize" = "1"
+	register "PcdDvfsEnable" = "1"
+	register "PcdCaMirrorEn" = "1"
+
+	############################################################
+	# Set the parameters for SiliconInit
+	############################################################
+
+	register "PcdSdcardMode" = "PCH_DISABLED"
+	register "PcdEnableHsuart0" = "0"
+	register "PcdEnableHsuart1" = "1"
+	register "PcdEnableAzalia" = "1"
+	register "PcdEnableXhci" = "1"
+	register "PcdEnableLpe" = "1"
+	register "PcdEnableDma0" = "1"
+	register "PcdEnableDma1" = "1"
+	register "PcdEnableI2C0" = "0"
+	register "PcdEnableI2C1" = "0"
+	register "PcdEnableI2C2" = "0"
+	register "PcdEnableI2C3" = "0"
+	register "PcdEnableI2C4" = "1"
+	register "PcdEnableI2C5" = "1"
+	register "PcdEnableI2C6" = "0"
+	register "PunitPwrConfigDisable" = "0"	# Enable SVID
+	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
+	register "PcdEmmcMode" = "PCH_ACPI_MODE"
+	register "PcdUsb3ClkSsc" = "1"
+	register "PcdDispClkSsc" = "1"
+	register "PcdSataClkSsc" = "1"
+	register "PcdEnableSata" = "0"		# Disable SATA
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "5"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "3"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "3"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "6"
+	register "Usb2Port3IUsbTxEmphasisEn" = "3"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "0"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
+	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
+	register "PcdSataInterfaceSpeed" = "3"
+	register "PcdPchSsicEnable" = "0"
+	register "PcdPchUsbHsicPort" = "0"
+	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
+	register "PMIC_I2CBus" = "1"
+	register "ISPEnable" = "0"		# Disable IUNIT
+	register "ISPPciDevConfig" = "3"
+	register "PcdSdDetectChk" = "0" # Disable SD card detect
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
+
+	# Enable devices in ACPI mode
+	register "lpss_acpi_mode" = "1"
+	register "emmc_acpi_mode" = "1"
+	register "sd_acpi_mode" = "1"
+	register "lpe_acpi_mode" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+					# EDS Table 24-4, Figure 24-5
+		device pci 00.0 on end	# 8086 2280 - SoC transaction router
+		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
+		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
+		device pci 0b.0 on end	# 8086 22dc - ?
+		device pci 10.0 on end	# 8086 2294 - MMC Port
+		device pci 11.0 off end	# 8086 0F15 - SDIO Port
+		device pci 12.0 off end	# 8086 0F16 - SD Port
+		device pci 13.0 off end	# 8086 22a3 - Sata controller
+		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
+		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
+		device pci 16.0 off end	# 8086 22b7 - USB device
+		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
+		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
+		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
+		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
+		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
+		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
+		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
+		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
+		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
+		device pci 1b.0 on end	# 8086 0F04 - HD Audio
+		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
+		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
+		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
+		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
+		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
+		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
+		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
+		device pci 1e.3 on end	# 8086 228a -   HSUART 1
+		device pci 1e.4 off end	# 8086 228c -   HSUART 2
+		device pci 1e.5 on end	# 8086 228e -   SPI 1
+		device pci 1e.6 off end	# 8086 2290 -   SPI 2
+		device pci 1e.7 off end	# 8086 22ac -   SPI 3
+		device pci 1f.0 on	# 8086 229c - LPC bridge
+			chip drivers/pc80/tpm
+				# Rising edge interrupt
+				register "irq_polarity" = "2"
+				device pnp 0c31.0 on
+					irq 0x70 = 10
+				end
+			end
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c
new file mode 100644
index 0000000000..6e81c23215
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/gpio.c
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright(C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/cyan/irqroute.h>
+#include <soc/gpio.h>
+#include <stdlib.h>
+
+/* South East Community */
+static const struct soc_gpio_map gpse_gpio_map[] = {
+	Native_M1,/* MF_PLT_CLK0 */
+	GPIO_NC, /* 01 PWM1 */
+	GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
+	GPIO_NC, /* 03 MF_PLT_CLK4 */
+	GPIO_NC, /* 04 MF_PLT_CLK3 */
+	GPIO_NC, /* PWM0 05 */
+	GPIO_NC, /* 06 MF_PLT_CLK5 */
+	GPIO_NC, /* 07 MF_PLT_CLK2 */
+	GPIO_NC, /* 15 SDMMC2_D3_CD_B */
+	Native_M1, /* 16 SDMMC1_CLK */
+	NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
+	GPIO_NC, /* 18 SDMMC2_D1 */
+	GPIO_NC, /* 19 SDMMC2_CLK */
+	NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
+	GPIO_NC, /* 21 SDMMC2_D2 */
+	GPIO_NC, /* 22 SDMMC2_CMD  */
+	NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
+	NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
+	GPIO_NC, /* 25 SDMMC2_D0 */
+	NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
+	GPIO_NC, /* 30 SDMMC3_D1 */
+	GPIO_NC, /* 31 SDMMC3_CLK */
+	GPIO_NC, /* 32 SDMMC3_D3 */
+	GPIO_NC, /* 33 SDMMC3_D2 */
+	GPIO_NC, /* 34 SDMMC3_CMD */
+	GPIO_NC, /* 35 SDMMC3_D0 */
+	NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
+	NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */
+	NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
+	Native_M1, /* 48 LPC_FRAMEB */
+	Native_M1, /* 49 MF_LPC_CLKOUT1 */
+	NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
+	Native_M1, /* 51 MF_LPC_CLKOUT0 */
+	NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
+	Native_M1,/* SPI1_MISO */
+	Native_M1, /* 61 SPI1_CS0_B */
+	Native_M1, /* SPI1_CLK */
+	NATIVE_PU20K(1), /* 63 MMC1_D6 */
+	Native_M1, /* 62 SPI1_MOSI */
+	NATIVE_PU20K(1), /* 65 MMC1_D5 */
+	GPIO_NC, /* SPI1_CS1_B  66 */
+	NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
+	NATIVE_PU20K(1), /* 68 MMC1_D7 */
+	GPIO_NC, /* 69 MMC1_RCLK */
+	Native_M1, /* 75  GPO USB_OC1_B */
+	Native_M1, /* 76  PMU_RESETBUTTON_B */
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	/* GPIO_ALERT 77   */
+	Native_M1, /* 78  SDMMC3_PWR_EN_B */
+	GPIO_NC, /* 79  GPI ILB_SERIRQ */
+	Native_M1, /* 80  USB_OC0_B */
+	GPIO_NC, /* 81  SDMMC3_CD_B */
+	GPIO_NC,  /* 82  spkr	 asummed gpio number */
+	Native_M1, /* 83 SUSPWRDNACK */
+	SPARE_PIN,/* 84 spare pin */
+	Native_M1, /* 85 SDMMC3_1P8_EN */
+	GPIO_END
+};
+
+
+/* South West Community */
+static const struct soc_gpio_map  gpsw_gpio_map[] = {
+	GPIO_NC, /* 00 FST_SPI_D2 */
+	Native_M1, /* 01 FST_SPI_D0 */
+	Native_M1, /* 02 FST_SPI_CLK */
+	GPIO_NC, /* 03 FST_SPI_D3 */
+	GPIO_NC, /* GPO FST_SPI_CS1_B */
+	Native_M1, /* 05 FST_SPI_D1 */
+	Native_M1, /* 06 FST_SPI_CS0_B */
+	GPIO_NC, /* 07 FST_SPI_CS2_B */
+	GPIO_NC, /* 15 UART1_RTS_B */
+	Native_M2, /* 16 UART1_RXD */
+	GPIO_NC, /* 17 UART2_RXD */
+	GPIO_NC, /* 18 UART1_CTS_B */
+	GPIO_NC, /* 19 UART2_RTS_B */
+	Native_M2, /* 20 UART1_TXD */
+	GPIO_NC, /* 21 UART2_TXD */
+	GPIO_NC, /* 22 UART2_CTS_B */
+	GPIO_NC, /* 30 MF_HDA_CLK */
+	GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
+	GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
+	GPIO_NC, /* 33 MF_HDA_SDO */
+	GPIO_NC, /* 34 MF_HDA_DOCKRSTB */
+	GPIO_NC, /* 35 MF_HDA_SYNC */
+	GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
+	GPIO_NC, /* 37 MF_HDA_DOCKENB */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
+	GPIO_NC, /* 49 I2C_NFC_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
+	GPIO_NC, /* 52 I2C_NFC_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
+	GPIO_NC, /* 61 I2C0_SDA */
+	GPIO_NC, /* 62 I2C2_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
+	GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
+	GPIO_NC, /* 65 I2C0_SCL */
+	GPIO_NC, /* 66 I2C2_SCL */
+	GPIO_INPUT_NO_PULL,/* 67  I2C3_SCL,RAMID1 */
+	GPIO_OUT_HIGH, /* 75 SATA_GP0 */
+	GPIO_NC,
+	/* 76 GPI SATA_GP1 */
+	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
+	GPIO_NC, /* 78 SATA_GP2 */
+	Native_M1, /* 79 MF_SMB_ALERTB */
+	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
+	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
+	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
+	GPIO_INPUT_PU_20K, /* 90 PCIE_CLKREQ0B */
+	GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
+	Native_M1, /* 92 GP_SSP_2_CLK */
+	NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
+	Native_M1, /* 94 GP_SSP_2_RXD */
+	GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
+	/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
+	Native_M1, /* 96 GP_SSP_2_FS */
+	NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
+	GPIO_END
+};
+
+
+/* North Community */
+static const struct soc_gpio_map  gpn_gpio_map[] = {
+	GPIO_NC, /* 00 GPIO_DFX0 */
+	GPIO_NC, /* 01 GPIO_DFX3 */
+	GPIO_NC, /* 02 GPIO_DFX7 */
+	GPIO_NC, /* 03 GPIO_DFX1 */
+	GPIO_NC, /* 04 GPIO_DFX5 */
+	GPIO_NC, /* 05 GPIO_DFX4 */
+	GPIO_NC, /* 06 GPIO_DFX8 */
+	GPIO_NC, /* 07 GPIO_DFX2 */
+	GPIO_NC, /* 08 GPIO_DFX6 */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
+	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
+	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+	/* 17 GPIO_SUS3 */
+	GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 18 GPIO_SUS7 */
+	GPIO_NC, /* 19 GPIO_SUS1 */
+	GPIO_NC, /* 20 GPIO_SUS5 */
+	GPIO_NC, /* 21 SEC_GPIO_SUS11 */
+	GPIO_NC, /* 22 GPIO_SUS4 */
+	GPIO_NC, /* 23 SEC_GPIO_SUS8 */
+	Native_M6, /* 24 GPIO_SUS2 */
+	GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
+	Native_M1, /* 26 CX_PREQ_B */
+	GPIO_NC, /* 27 SEC_GPIO_SUS9 */
+	Native_M1, /* 30 TRST_B */
+	Native_M1, /* 31 TCK */
+	GPIO_SKIP, /* 32 PROCHOT_B */
+	GPIO_SKIP, /* 33 SVID0_DATA */
+	Native_M1, /* 34 TMS */
+	GPIO_NC, /* 35 CX_PRDY_B_2 */
+	GPIO_NC, /* 36 TDO_2 */
+	Native_M1, /* 37 CX_PRDY_B */
+	GPIO_SKIP, /* 38 SVID0_ALERT_B */
+	Native_M1, /* 39 TDO */
+	GPIO_SKIP, /* 40 SVID0_CLK */
+	Native_M1, /* 41 TDI */
+	Native_M2, /* 45 GP_CAMERASB05 */
+	Native_M2, /* 46 GP_CAMERASB02 */
+	Native_M2, /* 47 GP_CAMERASB08 */
+	Native_M2, /* 48 GP_CAMERASB00 */
+	Native_M2, /* 49 GP_CAMERASBO6 */
+	GPIO_NC, /* 50 GP_CAMERASB10 */
+	Native_M2, /* 51 GP_CAMERASB03 */
+	GPIO_NC, /* 52 GP_CAMERASB09 */
+	Native_M2, /* 53 GP_CAMERASB01 */
+	Native_M2, /* 54 GP_CAMERASB07 */
+	GPIO_NC, /* 55 GP_CAMERASB11 */
+	Native_M2, /* 56 GP_CAMERASB04 */
+	GPIO_NC, /* 60 PANEL0_BKLTEN */
+	GPIO_NC, /* 61 HV_DDI0_HPD */
+	NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
+	Native_M1, /* 63 PANEL1_BKLTCTL */
+	NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
+	GPIO_NC, /* 65 PANEL0_BKLTCTL */
+	GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
+	NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
+	NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
+	Native_M1, /* 69 PANEL1_VDDEN */
+	Native_M1, /* 70 PANEL1_BKLTEN */
+	GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
+	GPIO_NC, /* 72 PANEL0_VDDEN */
+	GPIO_END
+};
+
+
+/* East Community */
+static const struct soc_gpio_map  gpe_gpio_map[] = {
+	Native_M1, /* 00 PMU_SLP_S3_B */
+	GPIO_NC, /* 01 PMU_BATLOW_B */
+	Native_M1, /* 02 SUS_STAT_B */
+	Native_M1, /* 03 PMU_SLP_S0IX_B */
+	Native_M1, /* 04 PMU_AC_PRESENT */
+	Native_M1, /* 05 PMU_PLTRST_B */
+	Native_M1, /* 06 PMU_SUSCLK */
+	GPIO_NC, /* 07 PMU_SLP_LAN_B */
+	Native_M1, /* 08 PMU_PWRBTN_B */
+	Native_M1, /* 09 PMU_SLP_S4_B */
+	NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
+	GPIO_NC, /* 11 PMU_WAKE_LAN_B */
+	GPIO_NC, /* 15 MF_GPIO_3 */
+	GPIO_NC, /* 16 MF_GPIO_7 */
+	GPIO_NC, /* 17 MF_I2C1_SCL */
+	GPIO_NC, /* 18 MF_GPIO_1 */
+	GPIO_NC, /* 19 MF_GPIO_5 */
+	GPIO_NC, /* 20 MF_GPIO_9 */
+	GPIO_NC, /* 21 MF_GPIO_0 */
+	GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
+	GPIO_NC, /* 23 MF_GPIO_8 */
+	GPIO_NC, /* 24 MF_GPIO_2 */
+	GPIO_NC, /* 25 MF_GPIO_6 */
+	GPIO_NC, /* 26 MF_I2C1_SDA */
+	GPIO_END
+};
+
+
+static struct soc_gpio_config gpio_config = {
+	/* BSW */
+	.north = gpn_gpio_map,
+	.southeast = gpse_gpio_map,
+	.southwest  = gpsw_gpio_map,
+	.east = gpe_gpio_map
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..8f54bb69d6
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	45
+#define DPTF_TSR0_CRITICAL	75
+
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"R4303_CPU"
+#define DPTF_TSR1_PASSIVE	49
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	1
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	49
+#define DPTF_TSR2_CRITICAL	70
+
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 300, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		2000,	/* PowerLimitMinimum */
+		6200,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..217f77f09f
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Matt DeVillier
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <acpi/trackpad_elan.asl>
+
+/* Realtek audio codec */
+#include <acpi/codec_realtek.asl>
diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h
new file mode 100644
index 0000000000..d68aa13e01
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/cyan/irqroute.h>
+
+/*
+ * Calculation of gpio based irq.
+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
+ * Max direct irq (MAX_DIRECT_IRQ) is 114.
+ * Size of gpio banks are
+ * GPSW_SIZE = 98
+ * GPNC_SIZE = 73
+ * GPEC_SIZE = 27
+ * GPSE_SIZE = 86
+ */
+
+/* KBD: Gpio index in N bank */
+#define BOARD_I8042_GPIO_INDEX		17
+/* Audio: Gpio index in SW bank */
+#define JACK_DETECT_GPIO_INDEX		95
+/* SCI: Gpio index in N bank */
+#define BOARD_SCI_GPIO_INDEX		15
+/* Trackpad: Gpio index in N bank */
+#define BOARD_TRACKPAD_GPIO_INDEX	18
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          5
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+/* SD CARD gpio */
+#define SDCARD_CD			81
+
+#define AUDIO_CODEC_HID			"10EC5650"
+#define AUDIO_CODEC_CID			"10EC5650"
+#define AUDIO_CODEC_DDN			"RTEK Codec Controller "
+#define AUDIO_CODEC_I2C_ADDR		0x1A
+
+/* I2C data hold time */
+#define BOARD_I2C6_DATA_HOLD_TIME	0x2F
+
+#define DPTF_CPU_PASSIVE		88
+#define DPTF_CPU_CRITICAL		90
+
+#endif
diff --git a/src/mainboard/google/cyan/variants/edgar/spd_util.c b/src/mainboard/google/cyan/variants/edgar/spd_util.c
new file mode 100644
index 0000000000..61aa9a7108
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/spd_util.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2017 Matt DeVillier
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <mainboard/google/cyan/spd/spd_util.h>
+
+/*
+ *   0b0000 - 4GiB total - 2 x 2GiB Samsung K4E8E304EE-EGCE
+ *   0b0001 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8JTBLAR-NUD
+ *   0b0010 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE
+ *   0b0011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8JTBLAR-NUD
+ *   0b0100 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF
+ *   0b0101 - TBD
+ *   0b0110 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF
+ */
+
+int get_variant_spd_index(int ram_id, int *dual)
+{
+	/* Determine if single or dual channel memory system */
+	/* RAMID1 is deterministic for edgar */
+	*dual = ((ram_id > 1) & 0x1) ? 0 : 1;
+
+	/* Display the RAM type */
+	switch (ram_id) {
+	case 0:
+		printk(BIOS_DEBUG, "4GiB Samsung K4E8E304EE-EGCE\n");
+		break;
+	case 1:
+		printk(BIOS_DEBUG, "4GiB Hynix H9CCNNN8JTBLAR-NUD\n");
+		break;
+	case 2:
+		printk(BIOS_DEBUG, "2GiB Samsung K4E8E304EE-EGCE\n");
+		break;
+	case 3:
+		printk(BIOS_DEBUG, "2GiB Hynix H9CCNNN8JTBLAR-NUD\n");
+		break;
+	case 4:
+		printk(BIOS_DEBUG, "4GiB Samsung K4E8E324EB-EGCF\n");
+		break;
+	case 5:
+		printk(BIOS_DEBUG, "empty\n");
+		break;
+	case 6:
+		printk(BIOS_DEBUG, "2GiB Samsung K4E8E324EB-EGCF\n");
+		break;
+	}
+
+	/* 1:1 mapping between ram_id and spd_index for edgar */
+	return ram_id;
+}