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| author | Nathaniel Roach <nroach44@gmail.com> | 2017-09-09 19:58:08 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 16:19:06 +0000 |
| commit | 52f0871b23233ec7314cf778e5534d99dd85ff3d (patch) | |
| tree | 6baf5418796144f56fd72a36a131dc92d709d755 /src | |
| parent | 3670cc1bad12522e3f9eb86d923c52d4016f90e9 (diff) | |
| download | coreboot-52f0871b23233ec7314cf778e5534d99dd85ff3d.tar.xz | |
sb/intel/bd82x6x: Add time-stamp around ME DRAM update
Add a timestamp before and after waiting for the ME to acknowledge the
DRAM being ready.
This allows easier debugging during use of me_cleaner and/or alternate
ME images.
Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/commonlib/include/commonlib/timestamp_serialized.h | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me.c | 3 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 60feffed87..21a2e47f6a 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -77,6 +77,10 @@ enum timestamp_id { TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, + /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ + TS_ME_INFORM_DRAM_WAIT = 940, + TS_ME_INFORM_DRAM_DONE = 941, + /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, TS_FSP_MEMORY_INIT_END = 951, @@ -177,6 +181,10 @@ static const struct timestamp_id_to_name { { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, { TS_START_KERNEL, "jumping to kernel" }, + /* Intel ME related timestamps */ + { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, + { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, + /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, { TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" }, diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 607cd14911..b2e920056d 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -20,6 +20,7 @@ #include <device/pci_ids.h> #include <halt.h> #include <string.h> +#include <timestamp.h> #include "me.h" #include "pch.h" @@ -190,6 +191,7 @@ int intel_early_me_init_done(u8 status) meDID = did.uma_base | (1 << 28);// | (1 << 23); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID); + timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); udelay(1100); /* Must wait for ME acknowledgement */ @@ -200,6 +202,7 @@ int intel_early_me_init_done(u8 status) hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; millisec++; } + timestamp_add_now(TS_ME_INFORM_DRAM_DONE); me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); |