diff options
| author | sridhar <sridhar.siricilla@intel.com> | 2019-06-13 14:26:00 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-19 19:35:56 +0000 |
| commit | 685b377e7e56ed6a046204baf73c43d76a87f4b4 (patch) | |
| tree | 362959e7de664be355a4e742c60297bdffff3313 /src | |
| parent | ba5f318736d9ade42160932d4119c47867ae1f35 (diff) | |
| download | coreboot-685b377e7e56ed6a046204baf73c43d76a87f4b4.tar.xz | |
mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.
BUG=none
TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index e30da3af4d..429d5daca8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C/D/F + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C/D/F + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" |