mrc_wdt_ppi

5 files changed, 86 insertions, 122 deletions

diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index e199d05f6d..5671d10dc9 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -54,6 +54,7 @@ romstage-y += mrc_misc.c
 romstage-y += pei_mem.c
 romstage-y += do_raminit_frag.c
 romstage-y += mrc_frag_init_memory.c
+romstage-y += mrc_wdt.c
 postcar-y += memmap.c
 
 endif
diff --git a/src/northbridge/intel/haswell/mrc.asm b/src/northbridge/intel/haswell/mrc.asm
index 301df94d31..5ba0e74b80 100644
--- a/src/northbridge/intel/haswell/mrc.asm
+++ b/src/northbridge/intel/haswell/mrc.asm
@@ -34,7 +34,6 @@ extern mrc_pch_init
 extern dmi_check_link
 extern pei_get_platform_memsize
 extern pei_choose_ranges
-extern get_c3res
 
 ; PEI services
 extern PeiServiceGetBootMode
@@ -155,6 +154,12 @@ extern io_fffa49a0
 extern io_fffa4c0d
 extern load_usb
 
+;; mrc_wdt
+
+extern mrc_wdt_ppi
+
+;;
+
 mrc_entry:
 mov ecx, esp
 mov esp, 0xff800000
@@ -2568,7 +2573,7 @@ mov eax, dword [ecx + 0xc]
 mov dword [ebp - 0x486], eax
 mov eax, dword [ecx + 0x10]
 mov dword [ebp - 0x482], eax
-mov esi, ref_fffc9e70  ; mov esi, 0xfffc9e70
+mov esi, mrc_wdt_ppi
 movzx eax, word [ecx + 0x14]
 mov dword [ebp - 0x47a], 0xfed84000
 mov dword [ebp - 0x47e], eax
@@ -43560,111 +43565,6 @@ mov ebp, esp
 pop ebp
 ret
 
-fcn_fffc5b14:  ; not directly referenced
-push ebp
-mov ebp, esp
-call get_c3res
-mov edx, eax
-in eax, dx
-shr eax, 0xe
-and eax, 1
-pop ebp
-ret
-
-fcn_fffc5b27:  ; not directly referenced
-push ebp
-mov ebp, esp
-call get_c3res
-mov edx, eax
-in eax, dx
-test eax, 0x3f0000
-setne al
-pop ebp
-ret
-
-fcn_fffc5b3c:  ; not directly referenced
-push ebp
-mov byte [0xff7d7540], 1
-mov ebp, esp
-push ebx
-call get_c3res
-mov edx, eax
-in eax, dx
-mov ebx, eax
-and ebx, 0xffbf7fff
-call get_c3res
-movzx edx, ax
-mov eax, ebx
-out dx, eax
-pop ebx
-pop ebp
-ret
-
-fcn_fffc5b65:  ; not directly referenced
-push ebp
-mov ebp, esp
-call get_c3res
-mov edx, eax
-in eax, dx
-shr eax, 0x17
-and eax, 1
-pop ebp
-ret
-
-fcn_fffc5b78:  ; not directly referenced
-push ebp
-mov ebp, esp
-push ebx
-call get_c3res
-mov edx, eax
-in eax, dx
-mov ebx, eax
-and ebx, 0xffbf3fff
-call get_c3res
-movzx edx, ax
-mov eax, ebx
-out dx, eax
-pop ebx
-pop ebp
-ret
-
-fcn_fffc5b9a:  ; not directly referenced
-push ebp
-mov eax, 0x80000002
-mov ebp, esp
-push esi
-push ebx
-mov esi, dword [ebp + 8]
-dec esi
-cmp esi, 0x3fe
-ja short loc_fffc5bf2  ; ja 0xfffc5bf2
-call get_c3res
-mov edx, eax
-in eax, dx
-mov ebx, eax
-or eax, 0x40e000
-or bh, 0xe0
-cmp byte [0xff7d7540], 0
-cmove ebx, eax
-and ebx, 0xfffffc00
-call get_c3res
-or ebx, esi
-movzx edx, ax
-mov eax, ebx
-out dx, eax
-call get_c3res
-or ebx, 0x80000000
-movzx edx, ax
-mov eax, ebx
-out dx, eax
-xor eax, eax
-
-loc_fffc5bf2:  ; not directly referenced
-pop ebx
-pop esi
-pop ebp
-ret
-
 fcn_fffc5bf6:
 push ebp
 mov ebp, esp
@@ -48726,14 +48626,6 @@ dd 0x00000003
 dd 0x01010001
 dd 0x07010201
 
-ref_fffc9e70:
-dd fcn_fffc5b9a
-dd fcn_fffc5b65
-dd fcn_fffc5b78
-dd fcn_fffc5b3c
-dd fcn_fffc5b27
-dd fcn_fffc5b14
-
 ref_fffc9ef8:
 dd 0x05010400
 dd 0x07030602
diff --git a/src/northbridge/intel/haswell/mrc_misc.c b/src/northbridge/intel/haswell/mrc_misc.c
index dd3ad19706..cb3d5dad39 100644
--- a/src/northbridge/intel/haswell/mrc_misc.c
+++ b/src/northbridge/intel/haswell/mrc_misc.c
@@ -18,9 +18,3 @@ void dmi_check_link(void)
 		}
 	}
 }
-
-uint32_t get_c3res(void)
-{
-	uint32_t pmbase = pci_read_config32(PCH_LPC_DEV, PMBASE) & 0xfffc;
-	return pmbase + C3_RES;
-}
diff --git a/src/northbridge/intel/haswell/mrc_misc.h b/src/northbridge/intel/haswell/mrc_misc.h
index 3d4a6652a2..b3f57cedf2 100644
--- a/src/northbridge/intel/haswell/mrc_misc.h
+++ b/src/northbridge/intel/haswell/mrc_misc.h
@@ -1,3 +1,2 @@
 int dummy_func(void);
 void dmi_check_link(void);
-uint32_t get_c3res(void);
diff --git a/src/northbridge/intel/haswell/mrc_wdt.c b/src/northbridge/intel/haswell/mrc_wdt.c
new file mode 100644
index 0000000000..c0830f1342
--- /dev/null
+++ b/src/northbridge/intel/haswell/mrc_wdt.c
@@ -0,0 +1,78 @@
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <arch/io.h>
+#include <device/pci_ops.h>
+
+static uint8_t *status = (uint8_t *)0xff7d7540;
+
+int fcn_fffc5b14(void);
+int fcn_fffc5b27(void);
+void fcn_fffc5b3c(void);
+int fcn_fffc5b65(void);
+void fcn_fffc5b78(void);
+int fcn_fffc5b9a(uint32_t v);
+
+static uint32_t pm54(void)
+{
+	/* 0x54 is C3_RES, but it seems not in lynxpoint */
+	uint32_t pmbase = pci_read_config32(PCH_LPC_DEV, PMBASE) & 0xfffc;
+	return pmbase + 0x54;
+}
+
+int fcn_fffc5b14(void)
+{
+	uint32_t tmp = inl(pm54());
+	return ((tmp >> 14) & 1);
+}
+
+int fcn_fffc5b27(void)
+{
+	uint32_t tmp = inl(pm54());
+	return ((tmp & 0x3f0000)?1:0);
+}
+
+void fcn_fffc5b3c(void)
+{
+	*status = 1;
+	u32 tmp = inl(pm54()) & 0xffbf7fff;
+	outl(tmp, pm54());
+}
+
+int fcn_fffc5b65(void)
+{
+	u32 tmp = inl(pm54());
+	return ((tmp >> 0x17) & 1);
+}
+
+void fcn_fffc5b78(void)
+{
+	u32 tmp = inl(pm54()) & 0xffbf3fff;
+	outl(tmp, pm54());
+}
+
+int fcn_fffc5b9a(uint32_t v)
+{
+	v--;
+	if (v > 0x3fe)
+		return 0x80000002;
+	u32 tmp = inl(pm54());
+	if (*status == 0) {
+		tmp |= 0x40e000;
+	} else {
+		tmp |= 0xe000;
+	}
+	tmp &= 0xfffffc00;
+	tmp |= v;
+	outl(tmp, pm54());
+	tmp |= 0x80000000;
+	outl(tmp, pm54());
+	return 0;
+}
+
+const void* const mrc_wdt_ppi[6] = {
+	(const void*) fcn_fffc5b9a,
+	(const void*) fcn_fffc5b65,
+	(const void*) fcn_fffc5b78,
+	(const void*) fcn_fffc5b3c,
+	(const void*) fcn_fffc5b27,
+	(const void*) fcn_fffc5b14,
+};