AMD Mahogany Fam10 ACPI table fixes.

Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup.

Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/574
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 113 insertions, 101 deletions

diff --git a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl
index 7b581b4fd4..76a9bfade3 100644
--- a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl
+++ b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl
@@ -31,6 +31,8 @@ Scope(\_SB) {
 		/* NB devices */
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
@@ -57,22 +59,45 @@ Scope(\_SB) {
 		Package(){0x0007FFFF, 1, INTA, 0 },
 		Package(){0x0007FFFF, 2, INTB, 0 },
 		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		Package(){0x0009FFFF, 0, INTB, 0 },
+		Package(){0x0009FFFF, 1, INTC, 0 },
+		Package(){0x0009FFFF, 2, INTD, 0 },
+		Package(){0x0009FFFF, 3, INTA, 0 },
+
+		Package(){0x000AFFFF, 0, INTC, 0 },
+		Package(){0x000AFFFF, 1, INTD, 0 },
+		Package(){0x000AFFFF, 2, INTA, 0 },
+		Package(){0x000AFFFF, 3, INTB, 0 },
+
+		Package(){0x000BFFFF, 0, INTD, 0 },
+		Package(){0x000BFFFF, 1, INTA, 0 },
+		Package(){0x000BFFFF, 2, INTB, 0 },
+		Package(){0x000BFFFF, 3, INTC, 0 },
+
+		Package(){0x000CFFFF, 0, INTA, 0 },
+		Package(){0x000CFFFF, 1, INTB, 0 },
+		Package(){0x000CFFFF, 2, INTC, 0 },
+		Package(){0x000CFFFF, 3, INTD, 0 },
+
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices */
 		/* Bus 0, Dev 17 - SATA controller #2 */
 		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTA, 0 },
+		Package(){0x0011FFFF, 0, INTG, 0 },
 
 		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
 		 * EHCI, dev 18, 19 func 2 */
 		Package(){0x0012FFFF, 0, INTA, 0 },
 		Package(){0x0012FFFF, 1, INTB, 0 },
 		Package(){0x0012FFFF, 2, INTC, 0 },
+		Package(){0x0012FFFF, 3, INTD, 0 },
 
 		Package(){0x0013FFFF, 0, INTC, 0 },
 		Package(){0x0013FFFF, 1, INTD, 0 },
 		Package(){0x0013FFFF, 2, INTA, 0 },
+		Package(){0x0013FFFF, 3, INTB, 0 },
 
 		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
 
@@ -81,6 +106,12 @@ Scope(\_SB) {
 		Package(){0x0014FFFF, 1, INTB, 0 },
 		Package(){0x0014FFFF, 2, INTC, 0 },
 		Package(){0x0014FFFF, 3, INTD, 0 },
+
+/*		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+*/
 	})
 
 	Name(APR0, Package(){
@@ -129,11 +160,13 @@ Scope(\_SB) {
 		/* Package(){0x0009FFFF, 1, 0, 16 }, */
 		/* Package(){0x0009FFFF, 2, 0, 17 }, */
 		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+
 		/* Bus 0, Dev A - PCIe Bridge for network card */
 		Package(){0x000AFFFF, 0, 0, 18 },
 		/* Package(){0x000AFFFF, 1, 0, 16 }, */
 		/* Package(){0x000AFFFF, 2, 0, 17 }, */
 		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */
@@ -146,41 +179,34 @@ Scope(\_SB) {
 		Package(){0x0012FFFF, 0, 0, 16 },
 		Package(){0x0012FFFF, 1, 0, 17 },
 		Package(){0x0012FFFF, 2, 0, 18 },
+		Package(){0x0012FFFF, 3, 0, 19 },
 
 		Package(){0x0013FFFF, 0, 0, 18 },
 		Package(){0x0013FFFF, 1, 0, 19 },
 		Package(){0x0013FFFF, 2, 0, 16 },
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		/* Package(){0x00130004, 2, 0, 18 }, */
-		/* Package(){0x00130005, 3, 0, 19 }, */
+		Package(){0x0013FFFF, 3, 0, 17 },
 
 		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
 		Package(){0x0014FFFF, 0, 0, 16 },
 		Package(){0x0014FFFF, 1, 0, 17 },
 		Package(){0x0014FFFF, 2, 0, 18 },
 		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
 	})
 
 	Name(PR1, Package(){
 		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
+		Package(){0x0005FFFF, 0, INTC, 0 },
+		Package(){0x0005FFFF, 1, INTD, 0 },
+		Package(){0x0005FFFF, 2, INTA, 0 },
+		Package(){0x0005FFFF, 3, INTB, 0 },
 	})
 
 	Name(APR1, Package(){
 		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
 		Package(){0x0005FFFF, 0, 0, 18 },
 		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+		Package(){0x0005FFFF, 2, 0, 16 },
+		Package(){0x0005FFFF, 3, 0, 17 },
 	})
 
 	Name(PS2, Package(){
@@ -201,10 +227,10 @@ Scope(\_SB) {
 
 	Name(PS4, Package(){
 		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
 	})
 
 	Name(APS4, Package(){
@@ -272,10 +298,10 @@ Scope(\_SB) {
 
 	Name(APS9, Package(){
 		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
 	})
 	Name(PSa, Package(){
 		/* PCIe slot - Hooked to PCIe slot 10 */
@@ -288,9 +314,9 @@ Scope(\_SB) {
 	Name(APSa, Package(){
 		/* PCIe slot - Hooked to PCIe slot 10 */
 		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
 	})
 
 	Name(PCIB, Package(){
diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c
index 74f5612de1..1f7c2f7920 100644
--- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c
+++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010-2011 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -49,12 +50,33 @@ static void dump_mem(u32 start, u32 end)
 extern const unsigned char AmlCode[];
 extern const unsigned char AmlCode_ssdt[];
 
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-extern const unsigned char AmlCode_ssdt2[];
-extern const unsigned char AmlCode_ssdt3[];
-extern const unsigned char AmlCode_ssdt4[];
-extern const unsigned char AmlCode_ssdt5[];
-#endif
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+
+	/* TODO: More HT and other tables need to go into this table generation.
+	 * This should also be moved out to the silicon level if it can.
+	 */
+
+	return (unsigned long) (acpigen_get_current());
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -68,8 +90,8 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_create_madt_lapics(current);
 
 	/* Write SB700 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
-					   IO_APIC_ADDR, 0);
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 						current, 0, 0, 2, 0);
@@ -100,11 +122,6 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-	acpi_header_t *ssdtx;
-	void *p;
-	int i;
-#endif
 
 	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -186,62 +203,13 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_add_table(rsdp, slit);
 
 	/* SSDT */
-	current	  = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-	ssdt = (acpi_header_t *)current;
-	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot PSTATE/TOM SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
-	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
-	update_ssdt((void*)ssdt);
-	/* recalculate checksum */
-	ssdt->checksum = 0;
-	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
-	current = acpi_add_ssdt_pstates(rsdp, current);
-
-#if CONFIG_ACPI_SSDTX_NUM >= 1
-
-	/* same htio, but different position? We may have to copy,
-	change HCIN, and recalculate the checknum and add_table */
-
-	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
-		if((sysconf.pci1234[i] & 1) != 1 ) continue;
-		u8 c;
-		if (i < 7) {
-			c = (u8) ('4' + i - 1);
-		} else {
-			c = (u8) ('A' + i - 1 - 6);
-		}
-		current	  = ( current + 0x07) & -0x08;
-		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
-		ssdtx = (acpi_header_t *)current;
-		switch (sysconf.hcid[i]) {
-		case 1:
-			p = &AmlCode_ssdt2;
-			break;
-		case 2:
-			p = &AmlCode_ssdt3;
-			break;
-		case 3:	/* 8131 */
-			p = &AmlCode_ssdt4;
-			break;
-		default:
-			/* HTX no io apic */
-			p = &AmlCode_ssdt5;
-			break;
-		}
-		memcpy(ssdtx, p, sizeof(acpi_header_t));
-		current += ssdtx->length;
-		memcpy(ssdtx, p, ssdtx->length);
-		update_ssdtx((void *)ssdtx, i);
-		ssdtx->checksum = 0;
-		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
-		acpi_add_table(rsdp, ssdtx);
-	}
-#endif
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl
index 692699db5b..8bba547a48 100644
--- a/src/mainboard/amd/mahogany_fam10/dsdt.asl
+++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1168,7 +1168,7 @@ DefinitionBlock (
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+			External (TOM2)
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1421,7 +1421,7 @@ DefinitionBlock (
 						IRQNoFlags(){13}
 					})
 				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
+#if 0 /* defined by HPET table? */
 				Device(HPTM) {
 					Name(_HID,EISAID("PNP0103"))
 					Name(CRS,ResourceTemplate()	{
@@ -1436,6 +1436,7 @@ DefinitionBlock (
 						Return(CRS)
 					}
 				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
 			} /* end LIBR */
 
 			Device(HPBR) {
@@ -1546,6 +1547,7 @@ DefinitionBlock (
 
 				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
@@ -1585,12 +1587,14 @@ DefinitionBlock (
 					,,
 					PEBM
 				)
-
+#endif
+				/* memory space for PCI BARs below 4GB */
+				Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
 			}) /* End Name(_SB.PCI0.CRES) */
 
 			Method(_CRS, 0) {
 				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
+#if 0
 				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
 				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
 				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
@@ -1614,8 +1618,7 @@ DefinitionBlock (
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	ShiftLeft(TOM2, 20, Local0)
-				*	Subtract(Local0, 0x100000000, DMHL)
+				*	Subtract(TOM2, 0x100000000, DMHL)
 				* }
 				*/
 
@@ -1628,6 +1631,21 @@ DefinitionBlock (
 					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
 					Store(PBLN,EBML)
 				}
+#endif
+				CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+				CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+				/*
+				 * Declare memory between TOM1 and 4GB as available
+				 * for PCI MMIO.
+				 * Use ShiftLeft to avoid 64bit constant (for XP).
+				 * This will work even if the OS does 32bit arithmetic, as
+				 * 32bit (0x00000000 - TOM1) will wrap and give the same
+				 * result as 64bit (0x100000000 - TOM1).
+				 */
+				Store(TOM1, MM1B)
+				ShiftLeft(0x10000000, 4, Local0)
+				Subtract(Local0, TOM1, Local0)
+				Store(Local0, MM1L)
 
 				Return(CRES) /* note to change the Name buffer */
 			}  /* end of Method(_SB.PCI0._CRS) */