diff options
| author | Scott Duplichan <scott@notabs.org> | 2010-10-07 18:25:04 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2010-10-07 18:25:04 +0000 |
| commit | a3bd1b1b25bb3056a6cc092b7a17a383e119a21f (patch) | |
| tree | 08884b8ebb15b8d5d81d72fce64bdc63369b53ba /src | |
| parent | 6798b478027cb3fd44d52706ad69dee29bae19ba (diff) | |
| download | coreboot-a3bd1b1b25bb3056a6cc092b7a17a383e119a21f.tar.xz | |
RS780 function ProgK8TempMmioBase is setting a reserved
bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_cmn.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780_cmn.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c index 026341394a..22d80fcf32 100644 --- a/src/southbridge/amd/rs690/rs690_cmn.c +++ b/src/southbridge/amd/rs690/rs690_cmn.c @@ -206,7 +206,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) if (in_out) { pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x8); + 1) >> 8) & 0xffffff00) | 0x80); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, ((mmio_base_add + 0x10000000 - diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c index 65dbcb9703..e4eee3324c 100644 --- a/src/southbridge/amd/rs780/rs780_cmn.c +++ b/src/southbridge/amd/rs780/rs780_cmn.c @@ -204,7 +204,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) if (in_out) { pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x8); + 1) >> 8) & 0xffffff00) | 0x80); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, ((mmio_base_add + 0x10000000 - |