diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-12-07 02:10:06 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-20 16:54:39 +0000 |
| commit | bbff157df50fdaab8e825e13228387dabda3d47b (patch) | |
| tree | fa915a2d9f72964f33f1c4ab2ad37208f1afc79e /src | |
| parent | be6fd4c4b5684fae3fc859158fbb47ca152ffe10 (diff) | |
| download | coreboot-bbff157df50fdaab8e825e13228387dabda3d47b.tar.xz | |
mb/google/fizz: Enable mbox command for ISL VR c-state issue
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Fizz is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:65499724
BRANCH=None
TEST=Build and boot Fizz
Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 18031d67cd..db6c83f2ed 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -86,6 +86,10 @@ chip soc/intel/skylake register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround + # Intersil VR c-state issue workaround + # send VR mailbox command for IA/GT/SA rails + register "IslVrCmd" = "2" + register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" register "pirqc_routing" = "PCH_IRQ11" |