diff options
| author | Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> | 2019-03-26 15:38:04 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2019-06-21 00:06:02 +0000 |
| commit | c10af299aeed2a7d530fbabbaa55947d64712333 (patch) | |
| tree | 69e5e96372fa26c971208c7ad997e2a027314d4f /src | |
| parent | 863853cd2d8e01db2045e73d96c502e4ecba8ad1 (diff) | |
| download | coreboot-c10af299aeed2a7d530fbabbaa55947d64712333.tar.xz | |
mediatek/mt8183: Calibrate vsim2 to 2.7 V
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.
BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter
Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/kukui/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/mt6358.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/mt6358.c | 41 |
3 files changed, 45 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index baaca43b90..1465243f07 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -29,6 +29,8 @@ void platform_romstage_main(void) mainboard_early_init(); mt6358_init(); + /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ + pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); mt_mem_init(get_sdram_config()); diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 02937bac9a..277ee9aa35 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -27,6 +27,7 @@ enum { PMIC_CPSDSA4 = 0x0a2e, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VSIM2_ANA_CON0 = 0x1e30, }; struct pmic_setting { @@ -38,5 +39,6 @@ struct pmic_setting { void mt6358_init(void); void pmic_set_power_hold(bool enable); +void pmic_set_vsim2_cali(unsigned int vsim2_mv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 705424337f..ea4274f14b 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <console/console.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> @@ -733,6 +734,46 @@ void pmic_set_power_hold(bool enable) pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); } +void pmic_set_vsim2_cali(unsigned int vsim2_mv) +{ + u16 vsim2_reg, cali_mv; + + cali_mv = vsim2_mv % 100; + assert(cali_mv % 10 == 0); + + switch (vsim2_mv - cali_mv) { + case 1700: + vsim2_reg = 0x3; + break; + + case 1800: + vsim2_reg = 0x4; + break; + + case 2700: + vsim2_reg = 0x8; + break; + + case 3000: + vsim2_reg = 0xb; + break; + + case 3100: + vsim2_reg = 0xc; + break; + + default: + assert(0); + return; + }; + + /* [11:8]=0x8, RG_VSIM2_VOSEL */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, vsim2_reg, 0xF, 8); + + /* [3:0], RG_VSIM2_VOCAL */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ |