mrc_init_memory from ghidra

11 files changed, 416 insertions, 641 deletions

diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 65b60a7bad..d9f02526df 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -34,10 +34,11 @@ smm-y += finalize.c
 romstage-libs += $(obj)/mrc.o
 romstage-libs += $(obj)/me_uma.o
 romstage-libs += $(obj)/pei_cpuio.o
-romstage-libs += $(obj)/mrc_init_memory.o
 romstage-libs += $(obj)/mrc_end_of_pei.o
 romstage-libs += $(obj)/pei_smbus.o
 romstage-libs += $(obj)/udiv.o
+romstage-libs += $(obj)/init_txt.o
+romstage-libs += $(obj)/fffcbf28.o
 $(obj)/%.o: $(src)/northbridge/intel/haswell/%.asm
 	echo "NASM $@"
 	nasm -f elf32 -o $@ $<
@@ -61,6 +62,7 @@ romstage-y += mrc_frags.c
 romstage-y += pei_usb.c
 romstage-y += me_uma.c
 romstage-y += mrc_init_memory_fcns.c
+romstage-y += mrc_init_memory.c
 postcar-y += memmap.c
 
 endif
diff --git a/src/northbridge/intel/haswell/fffcbf28.asm b/src/northbridge/intel/haswell/fffcbf28.asm
new file mode 100644
index 0000000000..a68b9cea93
--- /dev/null
+++ b/src/northbridge/intel/haswell/fffcbf28.asm
@@ -0,0 +1,213 @@
+global ref_fffcbf28
+
+extern fcn_fffaa884
+extern fcn_fffaa6af
+extern fcn_fffa78a0
+extern fcn_fffb8689
+extern fcn_fffa782c
+extern fcn_fffa7a1c
+extern fcn_fffa56ac
+extern fcn_fffc7720
+extern fcn_fffbd7da
+extern fcn_fffb8c0b
+extern fcn_fffb3f6c
+extern fcn_fffab4c0
+extern fcn_fffbd5ac
+extern fcn_fffa94dd
+extern fcn_fffae06c
+extern fcn_fffba408
+extern fcn_fffb8625
+extern fcn_fffae02a
+extern fcn_fffb8d2d
+extern fcn_fffb5763
+extern fcn_fffb5cbc
+extern fcn_fffb5535
+extern fcn_fffb5c9f
+extern fcn_fffb58c8
+extern fcn_fffb5a70
+extern fcn_fffb5811
+extern fcn_fffb59af
+extern fcn_fffb568f
+extern fcn_fffb514c
+extern fcn_fffb89f8
+extern fcn_fffad6f1
+extern fcn_fffaddd4
+extern fcn_fffbb819
+extern fcn_fffadf82
+extern fcn_fffb85ca
+extern fcn_fffadfcf
+extern fcn_fffae80e
+extern fcn_fffb365a
+extern fcn_fffae04b
+extern fcn_fffb2e66
+extern fcn_fffb8040
+extern fcn_fffb8d2d
+extern fcn_fffa7ecd
+extern fcn_fffab280
+extern fcn_fffa948c
+extern fcn_fffbd4c2
+extern fcn_fffa7e78
+extern fcn_fffaacb1
+extern fcn_fffa7e71
+extern fcn_fffaa9d1
+extern fcn_fffa8fb6
+extern dummy_func
+
+ref_fffcbf28:
+dd fcn_fffaa884
+dd 0x0000dd1b
+dd 0xff320000
+dd fcn_fffaa6af
+dd 0x0001dd1c
+dd 0xff3e0000
+dd dummy_func
+dd 0x0004dd1e
+dd 0xff3f0000
+dd fcn_fffa78a0
+dd 0x0005dd1f
+dd 0xff3f0000
+dd fcn_fffb8689
+dd 0x0003dd20
+dd 0xff310000
+dd fcn_fffa782c
+dd 0x0006dd21
+dd 0xff3f0000
+dd fcn_fffa7a1c
+dd 0x0007dd22
+dd 0xff3f0000
+dd fcn_fffa56ac
+dd 0x0008dd23
+dd 0xff3f0000
+dd fcn_fffc7720
+dd 0x0009dd24
+dd 0xff3f0000
+dd fcn_fffbd7da
+dd 0x000add26
+dd 0xff330000
+dd fcn_fffb8c0b
+dd 0x000bdd27
+dd 0xff330000
+dd fcn_fffb3f6c
+dd 0x000fdd29
+dd 0xff310000
+dd fcn_fffab4c0
+dd 0x000ddd28
+dd 0xff310000
+dd fcn_fffbd5ac
+dd 0x000edd25
+dd 0xff330000
+dd fcn_fffa94dd
+dd 0x0011dd2b
+dd 0xff310000
+dd fcn_fffae06c
+dd 0x0010dd2a
+dd 0xff310000
+dd fcn_fffba408
+dd 0x0012dd2c
+dd 0xff310000
+dd fcn_fffb8625
+dd 0x0014dd2e
+dd 0xff310000
+dd fcn_fffae02a
+dd 0x0015dd2f
+dd 0xff310000
+dd fcn_fffb8d2d
+dd 0x0020dd49
+dd 0xff310000
+dd fcn_fffb5763
+dd 0x0016dd46
+dd 0xff310000
+dd fcn_fffb5cbc
+dd 0x0017dd30
+dd 0xff310000
+dd fcn_fffb5535
+dd 0x0018dd30
+dd 0xff310000
+dd fcn_fffb5c9f
+dd 0x0019dd32
+dd 0xff310000
+dd fcn_fffb58c8
+dd 0x001bdd33
+dd 0xff310000
+dd fcn_fffb5a70
+dd 0x001cdd35
+dd 0xff310000
+dd fcn_fffb5811
+dd 0x001add45
+dd 0xff310000
+dd fcn_fffb59af
+dd 0x001edd37
+dd 0xff310000
+dd fcn_fffb568f
+dd 0x001ddd36
+dd 0xff310000
+dd fcn_fffb514c
+dd 0x001fdd41
+dd 0xff310000
+dd fcn_fffb89f8
+dd 0x0032dd3d
+dd 0xff310000
+dd fcn_fffad6f1
+dd 0x0026dd3e
+dd 0xff310000
+dd fcn_fffaddd4
+dd 0x0023dd3a
+dd 0xff310000
+dd fcn_fffbb819
+dd 0x0024dd3b
+dd 0xff310000
+dd fcn_fffadf82
+dd 0x0025dd3c
+dd 0xff310000
+dd fcn_fffb85ca
+dd 0x0021dd38
+dd 0xff310000
+dd fcn_fffadfcf
+dd 0x0022dd39
+dd 0xff310000
+dd fcn_fffae80e
+dd 0x0027dd3f
+dd 0xff310000
+dd fcn_fffb365a
+dd 0x0028dd40
+dd 0xff310000
+dd fcn_fffae04b
+dd 0x0029dd47
+dd 0xff310000
+dd fcn_fffb2e66
+dd 0x003bdd58
+dd 0x01310000
+dd fcn_fffb8040
+dd 0x002bdd44
+dd 0xff310000
+dd fcn_fffb8d2d
+dd 0x0020dd49
+dd 0xff310000
+dd fcn_fffa7ecd
+dd 0x0033dd50
+dd 0xff310000
+dd fcn_fffab280
+dd 0x002add42
+dd 0xff310000
+dd fcn_fffa948c
+dd 0x002ddd43
+dd 0xff3e0000
+dd fcn_fffbd4c2
+dd 0x002edd70
+dd 0xff3c0000
+dd fcn_fffa7e78
+dd 0x002fdd71
+dd 0xff3e0000
+dd fcn_fffaacb1
+dd 0x0030dd5b
+dd 0xff310000
+dd fcn_fffa7e71
+dd 0x002cdd5f
+dd 0xff310000
+dd fcn_fffaa9d1
+dd 0x0031dd5c
+dd 0xff330000
+dd fcn_fffa8fb6
+dd 0x0034dd5d
+dd 0xff3f0000
+
diff --git a/src/northbridge/intel/haswell/init_txt.asm b/src/northbridge/intel/haswell/init_txt.asm
new file mode 100644
index 0000000000..a779a3645f
--- /dev/null
+++ b/src/northbridge/intel/haswell/init_txt.asm
@@ -0,0 +1,14 @@
+global initialize_txt
+
+initialize_txt:
+push ebx
+mov edx, cr4
+mov eax, edx
+or eax, 0x4000 ; cr4 bit 14: Safer Mode Extensions Enable
+mov cr4, eax
+xor eax, eax
+mov ebx, eax
+getsec
+mov cr4, edx
+pop ebx
+ret
diff --git a/src/northbridge/intel/haswell/me_uma.c b/src/northbridge/intel/haswell/me_uma.c
index 19cf744404..10af7ca973 100644
--- a/src/northbridge/intel/haswell/me_uma.c
+++ b/src/northbridge/intel/haswell/me_uma.c
@@ -5,15 +5,9 @@
 #include <console/console.h>
 #include "mrc_sku.h"
 #include "mrc_wdt.h"
+#include "me_uma.h"
 
-u32 get_uma_size(EFI_PEI_SERVICES **pps, void *me);
-int fcn_fffbe070(const EFI_PEI_SERVICES **pps, void *me, u8 *a2);
-int fcn_fffbe110(const EFI_PEI_SERVICES **pps, u32, u8);
-int fcn_fffbe14d(const EFI_PEI_SERVICES **pps, void *me, int a3, u32 a4);
-int __attribute((regparm(2)))
-fcn_fffbdf70(const EFI_PEI_SERVICES **pps, int v);
-
-u32 get_uma_size(EFI_PEI_SERVICES **pps, void *me)
+u32 get_uma_size(const EFI_PEI_SERVICES **pps, void *me)
 {
 	int i = 0;
 	u32 me_uma;
diff --git a/src/northbridge/intel/haswell/me_uma.h b/src/northbridge/intel/haswell/me_uma.h
new file mode 100644
index 0000000000..214b1a6ccb
--- /dev/null
+++ b/src/northbridge/intel/haswell/me_uma.h
@@ -0,0 +1,11 @@
+#ifndef ME_UMA_H_3289n8t983t
+#define ME_UMA_H_3289n8t983t
+
+u32 get_uma_size(const EFI_PEI_SERVICES **pps, void *me);
+int fcn_fffbe070(const EFI_PEI_SERVICES **pps, void *me, u8 *a2);
+int fcn_fffbe110(const EFI_PEI_SERVICES **pps, u32, u8);
+int fcn_fffbe14d(const EFI_PEI_SERVICES **pps, void *me, int a3, u32 a4);
+int __attribute((regparm(2)))
+fcn_fffbdf70(const EFI_PEI_SERVICES **pps, int v);
+
+#endif
diff --git a/src/northbridge/intel/haswell/mrc_frag_init_memory.c b/src/northbridge/intel/haswell/mrc_frag_init_memory.c
index 7e5d07f58e..73e3a1280a 100644
--- a/src/northbridge/intel/haswell/mrc_frag_init_memory.c
+++ b/src/northbridge/intel/haswell/mrc_frag_init_memory.c
@@ -4,11 +4,10 @@
 #include <cpu/x86/msr.h>
 #include "mrc_utils.h"
 #include <arch/cpu.h>
-#include "pei_ram.h"
 #include <console/console.h>
 #include "mrc_misc.h"
+#include "mrc_init_memory.h"
 
-int frag_fffc1d20(void);
 int frag_fffc1d20(void)
 {
 	u32 tmp = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xa0);
@@ -17,7 +16,6 @@ int frag_fffc1d20(void)
 	return (tmp == 0xa0)?1:0;
 }
 
-int frag_fffc1fc3(void);
 int frag_fffc1fc3(void)
 {
 	u32 tmp = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xa0);
@@ -28,7 +26,6 @@ int frag_fffc1fc3(void)
 
 extern EFI_GUID mEfiMemoryRestoreDataGuid;
 
-void *create_raminit_hob(void);
 void *create_raminit_hob(void)
 {
 	void *hob;
@@ -98,7 +95,6 @@ static void set_cpuid(struct cpu_model_id *mycpu)
 	}
 }
 
-int test_memory(void);
 int test_memory(void)
 {
 	for (size_t i = 0; i < 0x1000; i++) {
@@ -114,7 +110,6 @@ int test_memory(void)
 	return 0;
 }
 
-void frag_fffc1c07(void);
 int initialize_txt(void);
 void frag_fffc1c07()
 {
@@ -145,7 +140,6 @@ static void * frag_fffc1f53(uint32_t *wb)
 	return hob;
 }
 
-int copy_mrc_input(pei_raminit_ppi *ppi, int bootmode, void* dst);
 int copy_mrc_input(pei_raminit_ppi *ppi, int bootmode, void* dst)
 {
 	void *inp = ppi->mrc_input;
@@ -161,7 +155,6 @@ int copy_mrc_input(pei_raminit_ppi *ppi, int bootmode, void* dst)
 	return 1;
 }
 
-void __attribute((regparm(1))) fcn_fffa9196(void *a);
 static int check_data_structs(void *ram_data, pei_raminit_ppi *ppi)
 {
 	uint32_t chk;
@@ -228,11 +221,6 @@ static int frag_fffc1ea8(void *ram_data, pei_raminit_ppi *ppi,
 	return 2;
 }
 
-int __attribute((regparm(3))) fcn_fffa1d20(int bootmode, int v, void *addr,
-		EFI_PEI_SERVICES **pps /* not used */, void *raminit_ppi);
-
-int superfrag_fffc1ea8(int bootmode, void *ram_data, pei_raminit_ppi *ppi,
-		uint32_t v50c4, uint8_t bl);
 int superfrag_fffc1ea8(int bootmode, void *ram_data, pei_raminit_ppi *ppi,
 		uint32_t v50c4, uint8_t bl)
 {
@@ -264,7 +252,6 @@ extern ram_st ref_fffcbf28[];
 int __attribute((regparm(3))) fcn_fffc6438(void *ram_data, u32 a, u32 b);
 void fcn_fffc6986(void);
 
-int frag_fffc2026(void *ram_data);
 int frag_fffc2026(void *ram_data)
 {
 	uint32_t tmp;
diff --git a/src/northbridge/intel/haswell/mrc_init_memory.asm b/src/northbridge/intel/haswell/mrc_init_memory.asm
deleted file mode 100644
index abf8b4ecef..0000000000
--- a/src/northbridge/intel/haswell/mrc_init_memory.asm
+++ /dev/null
@@ -1,614 +0,0 @@
-global mrc_init_memory
-
-extern mrc_zeromem
-extern mrc_memcpy
-extern haswell_family_model
-extern haswell_stepping
-extern gEfiPeiReadOnlyVariablePpiGuid
-extern gEfiPeiStallPpiGuid
-extern gPchMeUmaPpiGuid
-extern ref_fffcd4a4
-extern ref_fffcd4e4
-
-extern fcn_fffa10df
-extern locate_hob
-extern fcn_fffa1d20
-extern fcn_fffa56ac
-extern fcn_fffa782c
-extern fcn_fffa7899
-extern fcn_fffa78a0
-extern fcn_fffa7a1c
-extern fcn_fffa7e71
-extern fcn_fffa7e78
-extern fcn_fffa7ecd
-extern fcn_fffa8fb6
-extern fcn_fffa9196
-extern fcn_fffa948c
-extern fcn_fffa94dd
-extern fcn_fffaa6af
-extern fcn_fffaa884
-extern fcn_fffaa9d1
-extern fcn_fffaacb1
-extern fcn_fffab280
-extern fcn_fffab4c0
-extern fcn_fffad6f1
-extern fcn_fffaddd4
-extern fcn_fffadf82
-extern fcn_fffadfcf
-extern fcn_fffae02a
-extern fcn_fffae04b
-extern fcn_fffae06c
-extern fcn_fffae80e
-extern fcn_fffb2e66
-extern fcn_fffb365a
-extern fcn_fffb3f6c
-extern fcn_fffb5038
-extern fcn_fffb514c
-extern fcn_fffb5535
-extern fcn_fffb568f
-extern fcn_fffb5763
-extern fcn_fffb5811
-extern fcn_fffb58c8
-extern fcn_fffb59af
-extern fcn_fffb5a70
-extern fcn_fffb5c9f
-extern fcn_fffb5cbc
-extern fcn_fffb8040
-extern fcn_fffb85ca
-extern fcn_fffb8625
-extern fcn_fffb8689
-extern fcn_fffb89f8
-extern fcn_fffb8c0b
-extern fcn_fffb8d2d
-extern fcn_fffba408
-extern fcn_fffbb819
-extern fcn_fffbd4c2
-extern fcn_fffbd5ac
-extern fcn_fffbd7da
-extern fcn_fffc6438
-extern fcn_fffc6986
-extern fcn_fffc7720
-extern rtc_wait
-
-extern frag_fffc1d20
-extern frag_fffc1fc3
-extern create_raminit_hob
-extern frag_fffc1c07
-extern test_memory
-global initialize_txt
-extern copy_mrc_input
-extern superfrag_fffc1ea8
-extern frag_fffc2026
-global ref_fffcbf28
-extern memcpy
-extern dummy_func
-extern mrc_get_bootmode
-extern mrc_locateppi
-
-; me_uma
-extern get_uma_size
-extern fcn_fffbe070
-extern fcn_fffbe14d
-
-initialize_txt:
-push ebx
-mov edx, cr4
-mov eax, edx
-or eax, 0x4000 ; cr4 bit 14: Safer Mode Extensions Enable
-mov cr4, eax
-xor eax, eax
-mov ebx, eax
-getsec
-mov cr4, edx
-pop ebx
-ret
-
-
-; mrc_init_memory(eax is **PeiServices)
-mrc_init_memory:
-push ebp
-mov edx, 0x5022
-mov ebp, esp
-push edi
-push esi
-push ebx
-lea esp, [esp - 0x50bc]
-mov dword [ebp - 0x50bc], eax
-lea eax, [ebp - 0x503a]
-call mrc_zeromem
-lea eax, [ebp - 0x5079]
-mov ecx, 0x3f
-mov edx, ref_fffcbee8
-mov dword [ebp - 0x38ce], eax
-call mrc_memcpy
-mov edx, dword [ebp - 0x50bc]
-
-push edi
-push edi
-lea edx, [ebp - 0x509c] ; stores boot mode
-push edx
-push dword [ebp - 0x50bc]
-call mrc_get_bootmode
-add esp, 0x10
-
-cmp dword [ebp - 0x509c], 0x11
-je short loc_fffc1bfd
-call create_raminit_hob
-mov dword [ebp - 0x50a0], eax
-jmp short loc_fffc1c07
-
-loc_fffc1bfd: ; boot mode is 3
-mov dword [ebp - 0x50a0], 0
-
-loc_fffc1c07:
-sub esp, 0xc
-mov esi, 1
-xor edi, edi
-lea edx, [ebp - 0x50a4]
-push edx
-push 0
-push 0
-push ref_fffcd4e4
-push dword [ebp - 0x50bc]
-call mrc_locateppi
-add esp, 0x20
-
-lea eax, [ebp - 0x503a]
-mov edx, 0xdd00
-call rtc_wait
-
-mov ecx, dword [ebp - 0x50bc]
-sub esp, 0xc
-lea edx, [ebp - 0x50a8]
-mov byte [ebp - 0x50aa], 0
-push edx
-push 0
-push 0
-push gEfiPeiReadOnlyVariablePpiGuid
-push ecx
-call mrc_locateppi
-add esp, 0x20
-
-call frag_fffc1c07
-
-loc_fffc1d20:
-cmp dword [ebp - 0x509c], 0x11
-mov dword [ebp - 0x50c4], 2
-je short loc_fffc1d5a  ; je 0xfffc1d5a
-call frag_fffc1d20
-mov dword [ebp - 0x50c4], eax
-
-loc_fffc1d5a:
-lea eax, [ebp - 0x5094]
-call fcn_fffa9196  ; call 0xfffa9196
-lea edx, [ebp - 0x5036]
-push edx
-push dword [ebp - 0x509c]
-push dword [ebp - 0x50a4] ; memory init ppi
-call copy_mrc_input
-add esp, 12
-
-cmp dword [ebp - 0x509c], 0x11
-jne short loc_fffc1dc2  ; jne 0xfffc1dc2
-test al, al
-mov eax, 0x8000000e
-je loc_fffc23a2  ; je 0xfffc23a2
-
-loc_fffc1dc2:
-mov ecx, dword [ebp - 0x50bc]
-mov eax, dword [ebp - 0x50c4]
-dec eax
-cmp eax, 1
-jbe short loc_fffc1e18
-push ecx
-lea eax, [ebp - 0x50aa]
-push eax
-push 0
-push dword [ebp - 0x50bc]
-call fcn_fffbe070 ; in me_uma.c
-add esp, 0x10
-
-mov al, 0
-cmp byte [ebp - 0x50aa], 1
-cmove ebx, eax
-
-loc_fffc1e18:
-
-push ebx
-push dword [ebp - 0x50c4]
-push dword [ebp - 0x50a4]
-lea eax, [ebp - 0x503a]
-push eax
-push dword [ebp - 0x509c]
-call superfrag_fffc1ea8
-add esp, 20
-mov edi, eax
-
-push 0
-push dword [ebp - 0x50bc]
-call get_uma_size
-mov dword [ebp - 0x3feb], eax
-add esp, 8
-
-loc_fffc1fc3:
-mov ecx, dword [ebp - 0x4015]
-test ecx, ecx
-jne short loc_fffc2000  ; jne 0xfffc2000
-
-; ecx needs to be saved
-mov esi, ecx
-call frag_fffc1fc3
-mov ecx, esi
-
-loc_fffc2000:
-lea eax, [ebp - 0x397c]
-mov dword [ebp - 0x3963], ecx
-call fcn_fffa9196  ; call 0xfffa9196
-
-lea eax, [ebp - 0x503a]
-push eax
-call frag_fffc2026
-mov ebx, eax
-add esp, 4
-
-cmp ebx, 0x16
-je loc_fffc21fe  ; je 0xfffc21fe
-ja short loc_fffc2151  ; ja 0xfffc2151
-test ebx, ebx
-je loc_fffc225d  ; je 0xfffc225d
-cmp ebx, 0x15
-jne loc_fffc2251  ; jne 0xfffc2251
-jmp short loc_fffc2186  ; jmp 0xfffc2186
-
-loc_fffc2151:
-cmp ebx, 0x17
-je short loc_fffc21b8  ; je 0xfffc21b8
-cmp ebx, 0x1b
-jne loc_fffc2251  ; jne 0xfffc2251
-lea eax, [ebp - 0x397c]
-mov edx, 0x395c
-call mrc_zeromem
-lea eax, [ebp - 0x5079]
-inc byte [ebp - 0x4022]
-mov dword [ebp - 0x38ce], eax
-jmp near loc_fffc225d  ; jmp 0xfffc225d
-
-loc_fffc2186:
-sub esp, 0xc
-lea ecx, [ebp - 0x50a9]
-push 0
-lea edx, [ebp - 0x5088]
-lea eax, [ebp - 0x503a]
-call fcn_fffb5038  ; call 0xfffb5038
-add esp, 0x10
-mov cl, byte [ebp - 0x3964]
-cmp byte [ebp - 0x50a9], cl
-jb short loc_fffc21b8  ; jb 0xfffc21b8
-jmp near loc_fffc2251  ; jmp 0xfffc2251
-
-loc_fffc21b8:
-cmp dword [ebp - 0x4015], 3
-jne short loc_fffc21ed  ; jne 0xfffc21ed
-push eax
-lea ecx, [ebp - 0x4062]
-xor edx, edx
-push eax
-push dword [ebp - 0x50a4]
-push dword [ebp - 0x50bc]
-mov eax, dword [ebp - 0x509c]
-call fcn_fffa1d20  ; call 0xfffa1d20
-mov dword [ebp - 0x4015], eax
-add esp, 0x10
-jmp short loc_fffc21f7  ; jmp 0xfffc21f7
-
-loc_fffc21ed:
-mov dword [ebp - 0x4015], 0
-
-loc_fffc21f7:
-mov ebx, 0x17
-jmp short loc_fffc225d  ; jmp 0xfffc225d
-
-loc_fffc21fe:
-push eax
-push eax
-push dword [ebp - 0x3feb]
-push dword [ebp - 0x391a]
-push 1
-push edi
-push 0
-push dword [ebp - 0x50bc]
-call fcn_fffbe14d ; in me_uma.c
-add esp, 0x20
-lea eax, [ebp - 0x503a]
-mov edx, 0xddfe
-call rtc_wait
-
-; ReportStatusCode is not used in mrc
-; mov edx, dword [ebp - 0x50bc]
-; push eax
-; push eax
-; mov eax, dword [edx]
-; push 0
-; push 0
-; push 0
-; push 0x51009
-; push 2
-; push edx
-; call dword [eax + 0x58]  ; ucall
-; add esp, 0x20
-
-loc_fffc2251:
-in al, 0x80
-or eax, 0xffffff80
-out 0x80, al
-jmp near loc_fffc239d  ; jmp 0xfffc239d
-
-loc_fffc225d:
-cmp ebx, 0x1b
-sete dl
-cmp ebx, 0x17
-sete al
-or dl, al
-jne loc_fffc1fc3  ; jne 0xfffc1fc3
-mov eax, 0x100
-in al, 0x84
-test edi, edi
-mov ecx, dword [ebp - 0x3feb]
-sete bl
-cmp byte [ebp - 0x50c4], 1
-sete al
-and eax, ebx
-neg eax
-and eax, 3
-cmp ecx, 0x20
-ja short loc_fffc22d0  ; ja 0xfffc22d0
-mov edx, dword [0xf0000060]
-and edx, 0xfc000000
-mov edx, dword [edx + 0xb0010]
-inc edx
-je short loc_fffc22d0  ; je 0xfffc22d0
-push esi
-movzx eax, al
-push esi
-push ecx
-push dword [ebp - 0x391a]
-push eax
-push edi
-push 0
-push dword [ebp - 0x50bc]
-call fcn_fffbe14d ; in me_uma.c
-add esp, 0x20
-
-loc_fffc22d0:
-cmp dword [ebp - 0x509c], 0x11
-je short loc_fffc2355  ; je 0xfffc2355
-cmp edi, 3
-sete dl
-xor eax, eax
-or dl, bl
-jne short loc_fffc22ea  ; jne 0xfffc22ea
-jmp short loc_fffc2311  ; jmp 0xfffc2311
-
-loc_fffc22ea:
-call test_memory
-or eax, eax
-jne loc_fffc238d
-
-loc_fffc2311:
-mov dword [ebp - 0x503a], 0xfd4
-push edx
-lea edx, [ebp - 0x503a]
-push 0x5022
-push edx
-mov edx, dword [ebp - 0x50a0]
-add edx, 0x18
-push edx
-call memcpy
-mov eax, dword [ebp - 0x50a0]
-mov edx, 1
-add eax, 0x503a
-call mrc_zeromem
-add esp, 0x10
-
-loc_fffc2355:
-lea eax, [ebp - 0x503a]
-mov edx, 0x55
-call rtc_wait
-xor eax, eax
-jmp short loc_fffc23a2  ; jmp 0xfffc23a2
-
-loc_fffc238d:
-mov edx, 0xd5
-lea eax, [ebp - 0x503a]
-call rtc_wait
-
-loc_fffc239d:
-mov eax, 0x80000007
-
-loc_fffc23a2:
-lea esp, [ebp - 0xc]
-pop ebx
-pop esi
-pop edi
-pop ebp
-ret
-
-
-ref_fffcbee8:
-dd 0x4000f001
-dd 0x02005a01
-dd 0x011800dc
-dd 0x9004005a
-dd 0xa0020801
-dd 0x01900500
-dd 0x00a00208
-dd 0xe000f010
-dd 0x11000001
-dd 0x01e000f0
-dd 0xc0200000
-dd 0x00018000
-dd 0x00c02100
-dd 0x00000180
-dd 0x2200be0b
-dd 0x00000001
-
-ref_fffcbf28:
-dd fcn_fffaa884
-
-ref_fffcbf2c:
-dd 0x0000dd1b
-dd 0xff320000
-dd fcn_fffaa6af
-dd 0x0001dd1c
-dd 0xff3e0000
-dd dummy_func
-dd 0x0004dd1e
-dd 0xff3f0000
-dd fcn_fffa78a0
-dd 0x0005dd1f
-dd 0xff3f0000
-dd fcn_fffb8689
-dd 0x0003dd20
-dd 0xff310000
-dd fcn_fffa782c
-dd 0x0006dd21
-dd 0xff3f0000
-dd fcn_fffa7a1c
-dd 0x0007dd22
-dd 0xff3f0000
-dd fcn_fffa56ac
-dd 0x0008dd23
-dd 0xff3f0000
-dd fcn_fffc7720
-dd 0x0009dd24
-dd 0xff3f0000
-dd fcn_fffbd7da
-dd 0x000add26
-dd 0xff330000
-dd fcn_fffb8c0b
-dd 0x000bdd27
-dd 0xff330000
-dd fcn_fffb3f6c
-dd 0x000fdd29
-dd 0xff310000
-dd fcn_fffab4c0
-dd 0x000ddd28
-dd 0xff310000
-dd fcn_fffbd5ac
-dd 0x000edd25
-dd 0xff330000
-dd fcn_fffa94dd
-dd 0x0011dd2b
-dd 0xff310000
-dd fcn_fffae06c
-dd 0x0010dd2a
-dd 0xff310000
-dd fcn_fffba408
-dd 0x0012dd2c
-dd 0xff310000
-dd fcn_fffb8625
-dd 0x0014dd2e
-dd 0xff310000
-dd fcn_fffae02a
-dd 0x0015dd2f
-dd 0xff310000
-dd fcn_fffb8d2d
-dd 0x0020dd49
-dd 0xff310000
-dd fcn_fffb5763
-dd 0x0016dd46
-dd 0xff310000
-dd fcn_fffb5cbc
-dd 0x0017dd30
-dd 0xff310000
-dd fcn_fffb5535
-dd 0x0018dd30
-dd 0xff310000
-dd fcn_fffb5c9f
-dd 0x0019dd32
-dd 0xff310000
-dd fcn_fffb58c8
-dd 0x001bdd33
-dd 0xff310000
-dd fcn_fffb5a70
-dd 0x001cdd35
-dd 0xff310000
-dd fcn_fffb5811
-dd 0x001add45
-dd 0xff310000
-dd fcn_fffb59af
-dd 0x001edd37
-dd 0xff310000
-dd fcn_fffb568f
-dd 0x001ddd36
-dd 0xff310000
-dd fcn_fffb514c
-dd 0x001fdd41
-dd 0xff310000
-dd fcn_fffb89f8
-dd 0x0032dd3d
-dd 0xff310000
-dd fcn_fffad6f1
-dd 0x0026dd3e
-dd 0xff310000
-dd fcn_fffaddd4
-dd 0x0023dd3a
-dd 0xff310000
-dd fcn_fffbb819
-dd 0x0024dd3b
-dd 0xff310000
-dd fcn_fffadf82
-dd 0x0025dd3c
-dd 0xff310000
-dd fcn_fffb85ca
-dd 0x0021dd38
-dd 0xff310000
-dd fcn_fffadfcf
-dd 0x0022dd39
-dd 0xff310000
-dd fcn_fffae80e
-dd 0x0027dd3f
-dd 0xff310000
-dd fcn_fffb365a
-dd 0x0028dd40
-dd 0xff310000
-dd fcn_fffae04b
-dd 0x0029dd47
-dd 0xff310000
-dd fcn_fffb2e66
-dd 0x003bdd58
-dd 0x01310000
-dd fcn_fffb8040
-dd 0x002bdd44
-dd 0xff310000
-dd fcn_fffb8d2d
-dd 0x0020dd49
-dd 0xff310000
-dd fcn_fffa7ecd
-dd 0x0033dd50
-dd 0xff310000
-dd fcn_fffab280
-dd 0x002add42
-dd 0xff310000
-dd fcn_fffa948c
-dd 0x002ddd43
-dd 0xff3e0000
-dd fcn_fffbd4c2
-dd 0x002edd70
-dd 0xff3c0000
-dd fcn_fffa7e78
-dd 0x002fdd71
-dd 0xff3e0000
-dd fcn_fffaacb1
-dd 0x0030dd5b
-dd 0xff310000
-dd fcn_fffa7e71
-dd 0x002cdd5f
-dd 0xff310000
-dd fcn_fffaa9d1
-dd 0x0031dd5c
-dd 0xff330000
-dd fcn_fffa8fb6
-dd 0x0034dd5d
-dd 0xff3f0000
-
diff --git a/src/northbridge/intel/haswell/mrc_init_memory.c b/src/northbridge/intel/haswell/mrc_init_memory.c
new file mode 100644
index 0000000000..925beb25d9
--- /dev/null
+++ b/src/northbridge/intel/haswell/mrc_init_memory.c
@@ -0,0 +1,147 @@
+#include <stdint.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <arch/io.h>
+#include "mrc_pei.h"
+#include "mrc_utils.h"
+#include "mrc_misc.h"
+#include "device/pci.h"
+#include "mrc_init_memory.h"
+#include "me_uma.h"
+
+const uint32_t ref_fffcbee8[] = {
+	0x4000f001,
+	0x02005a01,
+	0x011800dc,
+	0x9004005a,
+	0xa0020801,
+	0x01900500,
+	0x00a00208,
+	0xe000f010,
+	0x11000001,
+	0x01e000f0,
+	0xc0200000,
+	0x00018000,
+	0x00c02100,
+	0x00000180,
+	0x2200be0b,
+	0x00000001,
+};
+
+extern EFI_GUID ref_fffcd4e4;
+extern EFI_GUID gEfiPeiReadOnlyVariablePpiGuid;
+
+int __attribute((regparm(1))) mrc_init_memory(const EFI_PEI_SERVICES **pps)
+{
+	int iVar1;
+	uint8_t retv;
+	uint8_t bVar2;
+	int iVar3;
+	uint32_t uVar4;
+	uint8_t local_BL__1;
+	uint32_t local_50c8;
+	uint8_t local_50ae;
+	uint8_t local_50ad;
+	void *ro_var_ppi;
+	void *raminit_ppi;
+	void *ram_hob;
+	int bootmode;
+	uint32_t local_5098;
+	uint32_t local_508c;
+	uint8_t local_507d[63];
+	char ram_data[20514];
+
+	mrc_zeromem(ram_data, 0x5022);
+	*(void **)(ram_data + 5996) = local_507d;
+	mrc_memcpy(local_507d, ref_fffcbee8, 0x3f);
+	mrc_get_bootmode(pps, &bootmode);
+	if (bootmode == 0x11) {
+		ram_hob = (void *)0x0;
+	} else {
+		ram_hob = create_raminit_hob();
+	}
+	mrc_locateppi(pps, &ref_fffcd4e4, 0, 0, &raminit_ppi);
+	rtc_wait(ram_data, 0xdd00);
+	local_50ae = '\0';
+	mrc_locateppi(pps, &gEfiPeiReadOnlyVariablePpiGuid, 0, 0, &ro_var_ppi);
+	frag_fffc1c07();
+	local_50c8 = 2;
+	if (bootmode != 0x11) {
+		local_50c8 = frag_fffc1d20();
+	}
+	fcn_fffa9196(&local_5098);
+	retv = copy_mrc_input(raminit_ppi, bootmode, ram_data + 4);
+	local_BL__1 = retv;
+	if ((bootmode != 0x11) || (iVar3 = -0x7ffffff2, retv != '\0')) {
+		if (1 < local_50c8 - 1) {
+			fcn_fffbe070(pps, (void *)0x0, &local_50ae);
+			if (local_50ae == '\x01') {
+				local_BL__1 = 0;
+			}
+		}
+		iVar3 = superfrag_fffc1ea8(bootmode, ram_data, raminit_ppi, local_50c8,
+				local_BL__1);
+		*(uint32_t *)(ram_data + 4175) = get_uma_size(pps, (void *)0x0);
+		do {
+			iVar1 = *(uint32_t *)(ram_data + 4133);
+			if (iVar1 == 0) {
+				frag_fffc1fc3();
+			}
+			*(uint32_t *)(ram_data + 5847) = iVar1;
+			fcn_fffa9196((uint32_t *)(ram_data + 0x16be));
+			uVar4 = frag_fffc2026(ram_data);
+			if (uVar4 == 0x16) {
+				fcn_fffbe14d(pps, (void *)0x0, iVar3, 1);
+				rtc_wait(ram_data, 0xddfe);
+loc_fffc2251:
+				bVar2 = inb(0x80);
+				outb(bVar2 | 0x80, 0x80);
+				return -0x7ffffff9;
+			}
+			if (uVar4 < 0x17) {
+				if (uVar4 != 0) {
+					if ((uVar4 != 0x15)
+							|| (fcn_fffb5038(ram_data, &local_508c, &local_50ad,
+									NULL),
+								(uint8_t)ram_data[5846] <= local_50ad
+								/* what's this function?? */))
+						goto loc_fffc2251;
+loc_fffc21b8:
+					if (*(uint32_t *)(ram_data + 4133) == 3) {
+						*(uint32_t *)(ram_data + 4133) = fcn_fffa1d20(
+								bootmode, 0, ram_data + 0xfd8, pps,
+								raminit_ppi);
+					} else {
+						*(uint32_t *)(ram_data + 4133) = 0;
+					}
+					uVar4 = 0x17;
+				}
+			} else {
+				if (uVar4 == 0x17)
+					goto loc_fffc21b8;
+				if (uVar4 != 0x1b)
+					goto loc_fffc2251;
+				mrc_zeromem(ram_data + 0x16be, 0x395c);
+				*(void **)(ram_data + 5996) = local_507d;
+				ram_data[4120] = ram_data[4120] + '\x01';
+			}
+		} while (uVar4 == 0x1b || uVar4 == 0x17);
+		inb(0x84);
+		if ((*(int32_t *)(ram_data + 4175) < 0x21)
+				&& pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) != -1) {
+			fcn_fffbe14d(pps, (void *)0x0, iVar3,
+					-(uint32_t)(iVar3 == 0 && (char)local_50c8 == '\x01') & 3);
+		}
+		if (bootmode != 0x11) {
+			if ((iVar3 == 3 || iVar3 == 0) && (iVar3 = test_memory(), iVar3 != 0)) {
+				rtc_wait(ram_data, 0xd5);
+				return -0x7ffffff9;
+			}
+			*(uint32_t *)(ram_data) = 0xfd4;
+			memcpy((void *)((int)ram_hob + 0x18), ram_data, 0x5022);
+			mrc_zeromem((void *)((int)ram_hob + 0x503a), 1);
+		}
+		rtc_wait(ram_data, 0x55);
+		iVar3 = 0;
+	}
+	return iVar3;
+}
diff --git a/src/northbridge/intel/haswell/mrc_init_memory.h b/src/northbridge/intel/haswell/mrc_init_memory.h
new file mode 100644
index 0000000000..f68a07fa0f
--- /dev/null
+++ b/src/northbridge/intel/haswell/mrc_init_memory.h
@@ -0,0 +1,21 @@
+#ifndef MRC_INIT_MEMORY_H
+#define MRC_INIT_MEMORY_H
+
+#include "pei_ram.h"
+
+int __attribute((regparm(1))) mrc_init_memory(const EFI_PEI_SERVICES **pps);
+
+int __attribute((regparm(3))) fcn_fffa1d20(int bootmode, int v, void *addr,
+		const EFI_PEI_SERVICES **pps /* not used */, void *raminit_ppi);
+void frag_fffc1c07(void);
+int frag_fffc1d20(void);
+int superfrag_fffc1ea8(int bootmode, void *ram_data, pei_raminit_ppi *ppi,
+		uint32_t v50c4, uint8_t bl);
+int frag_fffc1fc3(void);
+int frag_fffc2026(void *ram_data);
+void __attribute((regparm(1))) fcn_fffa9196(void *a);
+int copy_mrc_input(pei_raminit_ppi *ppi, int bootmode, void* dst);
+void *create_raminit_hob(void);
+int test_memory(void);
+
+#endif
diff --git a/src/northbridge/intel/haswell/mrc_init_memory_fcns.c b/src/northbridge/intel/haswell/mrc_init_memory_fcns.c
index 665a4fe159..fcaa7611bb 100644
--- a/src/northbridge/intel/haswell/mrc_init_memory_fcns.c
+++ b/src/northbridge/intel/haswell/mrc_init_memory_fcns.c
@@ -1,6 +1,5 @@
 #include "mrc_pei.h"
 
-void mrc_get_bootmode(const EFI_PEI_SERVICES **pps, int *bootmode);
 void mrc_get_bootmode(const EFI_PEI_SERVICES **pps, int *bootmode)
 {
 	(*pps)->GetBootMode(pps, bootmode);
@@ -8,9 +7,6 @@ void mrc_get_bootmode(const EFI_PEI_SERVICES **pps, int *bootmode)
 
 int mrc_locateppi(const EFI_PEI_SERVICES **pps,
 		const EFI_GUID *Guid, unsigned long instance,
-		EFI_PEI_PPI_DESCRIPTOR  **PpiDescriptor, void *ppi);
-int mrc_locateppi(const EFI_PEI_SERVICES **pps,
-		const EFI_GUID *Guid, unsigned long instance,
 		EFI_PEI_PPI_DESCRIPTOR  **PpiDescriptor, void *ppi)
 {
 	return (*pps)->LocatePpi(pps, Guid, instance, PpiDescriptor, ppi);
diff --git a/src/northbridge/intel/haswell/mrc_pei.h b/src/northbridge/intel/haswell/mrc_pei.h
index 3034ddac83..06dcb85a3f 100644
--- a/src/northbridge/intel/haswell/mrc_pei.h
+++ b/src/northbridge/intel/haswell/mrc_pei.h
@@ -192,4 +192,8 @@ MRC_PEI *PEI_FROM_PEI_SERVICE(const EFI_PEI_SERVICES *ps)
 	return pei;
 }
 
+void mrc_get_bootmode(const EFI_PEI_SERVICES **pps, int *bootmode);
+int mrc_locateppi(const EFI_PEI_SERVICES **pps,
+		const EFI_GUID *Guid, unsigned long instance,
+		EFI_PEI_PPI_DESCRIPTOR  **PpiDescriptor, void *ppi);
 #endif