soc/intel/quark: Set the UPD values for MemoryInit

Set the UPD values for MemoryInit.
*  Update the FspUpdVpd.h file which specifies the parameters for
   MemoryInit.
*  Add the necessary values to chip.h to enable values to come from
   the mainboard's devicetree.cb file
*  Add the parameters to the mainboard's devicetree.cb file
*  Locate the platform configuration database file (pdat.bin)
*  Copy the data values from the chip_info structure into the UPDs
*  Display the UPD values

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_DISPLAY_UPD_DATA=y
*  Testing successful when the UPD data is displayed before the call to
   MemoryInit

Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

5 files changed, 149 insertions, 71 deletions

diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index 52e019bc9e..c171aa0d6a 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -16,6 +16,16 @@
 
 chip soc/intel/quark
 
+	############################################################
+	# Set the parameters for MemoryInit
+	############################################################
+
+	register "PcdSmmTsegSize" = "0"	# SMM Region size in MiB
+
+	############################################################
+	# Enable the devices
+	############################################################
+
 	device domain 0 on
 					# EDS Table 3
 		device pci 00.0 on end	# 8086 0958 - Host Bridge
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
index 59c8793dfe..fc9890fde5 100644
--- a/src/soc/intel/quark/chip.h
+++ b/src/soc/intel/quark/chip.h
@@ -19,11 +19,21 @@
 #define _SOC_CHIP_H_
 
 #include <stdint.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
 struct soc_intel_quark_config {
-	uint32_t junk;
+	/*
+	 * MemoryInit:
+	 *
+	 * The following fields come from FspUpdVpd.h and are defined as PCDs
+         * for the FSP binary.  Data for these fields comes from the board's
+	 * devicetree.cb file which gets processed into static.c and then
+	 * built into the coreboot image.  The fields below contain retain
+	 * the FSP PCD field name.
+	 */
+	UINT16 PcdSmmTsegSize;
 };
 
 extern struct chip_operations soc_ops;
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index d776e1e7d7..4f577cef8e 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -18,6 +18,7 @@
 #ifndef _QUARK_PCI_DEVS_H_
 #define _QUARK_PCI_DEVS_H_
 
+#include <arch/io.h>
 #include <device/pci.h>
 #include <soc/QuarkNcSocId.h>
 
@@ -31,4 +32,8 @@
 # define HSUART1_DEV SIO1_DEV
 # define HSUART1_FUNC 5
 
+/* Platform Controller Unit */
+# define LPC_DEV_FUNC	PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, \
+				PCI_FUNCTION_NUMBER_QNC_LPC)
+
 #endif /* _QUARK_PCI_DEVS_H_ */
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 731e52975d..a089185bd0 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -13,9 +13,12 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+#define __SIMPLE_DEVICE__
 
 #include <arch/early_variables.h>
 #include <console/console.h>
+#include <cbfs.h>
+#include "../chip.h"
 #include <device/pci_def.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
@@ -47,3 +50,54 @@ struct chipset_power_state *fill_power_state(void)
 	printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
 	return ps;
 }
+
+/* Initialize the UPD parameters for MemoryInit */
+void soc_memory_init_params(struct romstage_params *params,
+			    MEMORY_INIT_UPD *upd)
+{
+	const struct device *dev;
+	char *pdat_file;
+	size_t pdat_file_len;
+	const struct soc_intel_quark_config *config;
+
+	/* Locate the pdat.bin file */
+	pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW,
+		&pdat_file_len);
+	if (!pdat_file) {
+		printk(BIOS_DEBUG,
+			"Platform configuration file (pdat.bin) not found.");
+		pdat_file_len = 0;
+	}
+
+	/* Locate the configuration data from devicetree.cb */
+	dev = dev_find_slot(0, LPC_DEV_FUNC);
+	if (!dev) {
+		printk(BIOS_ERR,
+			"Error! Device (PCI:0:%02x.%01x) not found, "
+			"soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
+			PCI_FUNCTION_NUMBER_QNC_LPC);
+		return;
+	}
+	config = dev->chip_info;
+
+	/* Set the parameters for MemoryInit */
+	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
+	upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+		config->PcdSmmTsegSize : 0;
+	upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file;
+	upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len;
+}
+
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+	MEMORY_INIT_UPD *new)
+{
+	/* Display the parameters for MemoryInit */
+	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
+	fsp_display_upd_value("PcdSmmTsegSize", 2,
+		old->PcdSmmTsegSize, new->PcdSmmTsegSize);
+	fsp_display_upd_value("PcdPlatformDataBaseAddress", 4,
+		old->PcdPlatformDataBaseAddress,
+		new->PcdPlatformDataBaseAddress);
+	fsp_display_upd_value("PcdPlatformDataMaxLen", 4,
+		old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen);
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
index 2a11b20515..b6b6cc4670 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -33,139 +33,138 @@ are permitted provided that the following conditions are met:
 #ifndef __FSPUPDVPD_H__
 #define __FSPUPDVPD_H__
 
-#pragma pack(push, 1)
+#pragma pack(1)
+
+
+//
+// TODO - Port to fit Quark SoC.
+//
 
 #define MAX_CHANNELS_NUM       2
 #define MAX_DIMMS_NUM          2
 
 typedef struct {
-  UINT8         DimmId;
-  UINT32        SizeInMb;
-  UINT16        MfgId;
-  UINT8         ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
+	UINT8         DimmId;
+	UINT32        SizeInMb;
+	UINT16        MfgId;
+	UINT8         ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
 } DIMM_INFO;
 
 typedef struct {
-  UINT8         ChannelId;
-  UINT8         DimmCount;
-  DIMM_INFO     DimmInfo[MAX_DIMMS_NUM];
+	UINT8         ChannelId;
+	UINT8         DimmCount;
+	DIMM_INFO     DimmInfo[MAX_DIMMS_NUM];
 } CHANNEL_INFO;
 
 typedef struct {
-  UINT8         Revision;
-  UINT16        DataWidth;
-  /** As defined in SMBIOS 3.0 spec
-    Section 7.18.2 and Table 75
-  **/
-  UINT8         MemoryType;
-  UINT16        MemoryFrequencyInMHz;
-  /** As defined in SMBIOS 3.0 spec
-    Section 7.17.3 and Table 72
-  **/
-  UINT8         ErrorCorrectionType;
-  UINT8         ChannelCount;
-  CHANNEL_INFO  ChannelInfo[MAX_CHANNELS_NUM];
+	UINT8         Revision;
+	UINT16        DataWidth;
+	/** As defined in SMBIOS 3.0 spec
+	Section 7.18.2 and Table 75
+	**/
+	UINT8         MemoryType;
+	UINT16        MemoryFrequencyInMHz;
+	/** As defined in SMBIOS 3.0 spec
+	Section 7.17.3 and Table 72
+	**/
+	UINT8         ErrorCorrectionType;
+	UINT8         ChannelCount;
+	CHANNEL_INFO  ChannelInfo[MAX_CHANNELS_NUM];
 } FSP_SMBIOS_MEMORY_INFO;
 
-/** UPD data structure for FspMemoryInitApi
-**/
-typedef struct {
 
+
+typedef struct {
 /** Offset 0x0020
 **/
   UINT64                      Signature;
-
-/** Offset 0x0028 - Revision
-  Revision version of the MemoryInitUpd Region
+/** Offset 0x0028
 **/
   UINT8                       Revision;
+/** Offset 0x0029
+    Tseg Size
+    Size of SMRAM memory reserved.
+**/
+  UINT8                       PcdSmmTsegSize;
+/** Offset 0x002A
+**/
+  UINT32                      PcdPlatformDataBaseAddress;
+/** Offset 0x002E
+**/
+  UINT32                      PcdPlatformDataMaxLen;
+/** Offset 0x0032
+**/
+  UINT8                       ReservedMemoryInitUpd[14];
 } MEMORY_INIT_UPD;
 
-/** UPD data structure for FspSiliconInitApi
-**/
 typedef struct {
-
-/** Offset 0x0200
+/** Offset 0x0040
 **/
   UINT64                      Signature;
-
-/** Offset 0x0208 - Revision
-  Revision version of the SiliconInitUpd Region
+/** Offset 0x0048
 **/
   UINT8                       Revision;
+/** Offset 0x0049
+**/
+  UINT8                       ReservedSiliconInitUpd[183];
 } SILICON_INIT_UPD;
 
 #define FSP_UPD_SIGNATURE                0x244450554B525124        /* '$QRKUPD$' */
 #define FSP_MEMORY_INIT_UPD_SIGNATURE    0x244450554D454D24        /* '$MEMUPD$' */
 #define FSP_SILICON_INIT_UPD_SIGNATURE   0x244450555F495324        /* '$SI_UPD$' */
 
-/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field.
-**/
-typedef struct {
-
+typedef struct _UPD_DATA_REGION {
 /** Offset 0x0000
 **/
   UINT64                      Signature;
-
-/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package.
-  Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+/** Offset 0x0008
 **/
   UINT8                       Revision;
-
 /** Offset 0x0009
 **/
   UINT8                       ReservedUpd0[7];
-
-/** Offset 0x0010 - MemoryInitUpdOffset
-  This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION
+/** Offset 0x0010
 **/
   UINT32                      MemoryInitUpdOffset;
-
-/** Offset 0x0014 - SiliconInitUpdOffset
-  This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION
+/** Offset 0x0014
 **/
   UINT32                      SiliconInitUpdOffset;
-
 /** Offset 0x0018
 **/
   UINT64                      ReservedUpd1;
-
 /** Offset 0x0020
 **/
   MEMORY_INIT_UPD             MemoryInitUpd;
-
-/** Offset 0x0200
+/** Offset 0x0040
 **/
   SILICON_INIT_UPD            SiliconInitUpd;
-
-/** Offset 0x03FA - RegionTerminator
-  This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field.
+/** Offset 0x0100
 **/
-  UINT16                      RegionTerminator;
+  UINT16                      PcdRegionTerminator;
 } UPD_DATA_REGION;
 
-#define FSP_IMAGE_ID    0x305053462D4B5551	/* 'QUK-FSP0' */
-#define FSP_IMAGE_REV   0x00000000		/* 0.0 */
-
-/** VPD data structure
-**/
-typedef struct {
+#define FSP_IMAGE_ID    0x305053462D4B5551        /* 'QUK-FSP0' */
+#define FSP_IMAGE_REV   0x00000000
 
+typedef struct _VPD_DATA_REGION {
 /** Offset 0x0000
 **/
   UINT64                      PcdVpdRegionSign;
-
-/** Offset 0x0008 - PcdImageRevision
-  This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package.  This should match the ImageRevision in FSP_INFO_HEADER.
+/** Offset 0x0008
+    PcdImageRevision
 **/
   UINT32                      PcdImageRevision;
-
-/** Offset 0x000C - PcdUpdRegionOffset
-  This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION.
+/** Offset 0x000C
 **/
   UINT32                      PcdUpdRegionOffset;
+/** Offset 0x0010
+**/
+  UINT8                       UnusedVpdSpace0[16];
+/** Offset 0x0020
+**/
+  UINT32                      PcdFspReservedMemoryLength;
 } VPD_DATA_REGION;
 
-#pragma pack(pop)
+#pragma pack()
 
 #endif