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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-09 13:33:39 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-10 03:24:23 +0000 |
| commit | ec558682fc11a985eb1b02b400a86ea9de407796 (patch) | |
| tree | 001c03edc8389648f484e9d36651c222d74fb0fa /src | |
| parent | 2dce9235244c15efa7c34762a0c47b1fa211ffad (diff) | |
| download | coreboot-ec558682fc11a985eb1b02b400a86ea9de407796.tar.xz | |
aopen/dxplplusu: Move timestamps to common code
First initialisation is already in cpu/intel/car/romstage.c.
Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/romstage.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.c | 5 |
2 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 75aad28093..f95c7f91e2 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <timestamp.h> #include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h> @@ -47,9 +46,6 @@ void mainboard_romstage_entry(unsigned long bist) }, }; - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Get the serial port running and print a welcome banner */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -61,15 +57,11 @@ void mainboard_romstage_entry(unsigned long bist) if (!e7505_mch_is_ready()) { enable_smbus(); - timestamp_add_now(TS_BEFORE_INITRAM); - /* The real MCH initialisation. */ e7505_mch_init(memctrl); /* Hook for post ECC scrub settings and debug. */ e7505_mch_done(memctrl); - - timestamp_add_now(TS_AFTER_INITRAM); } printk(BIOS_DEBUG, "SDRAM is up.\n"); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 6550bb5cb6..70a0d66950 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -37,6 +37,7 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> +#include <timestamp.h> #include "raminit.h" #include "e7505.h" @@ -1768,6 +1769,8 @@ void e7505_mch_init(const struct mem_controller *memctrl) RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); sdram_enable(memctrl); @@ -1777,6 +1780,8 @@ void e7505_mch_done(const struct mem_controller *memctrl) { sdram_post_ecc(memctrl); + timestamp_add_now(TS_AFTER_INITRAM); + RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); DUMPNORTH(); } |