x86/acpi_device: Add support for GPIO output polarity

Instead of hard-coding the polarity of the GPIO to active high/low,
accept it as a parameter in devicetree. This polarity can then be used
while calling into acpi_dp_add_gpio to determine the active low status
correctly.

BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that correct polarity is set for reset-gpio on reef.

Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

5 files changed, 21 insertions, 5 deletions

diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h
index 4b3a469199..b0285d2c23 100644
--- a/src/arch/x86/include/arch/acpi_device.h
+++ b/src/arch/x86/include/arch/acpi_device.h
@@ -110,6 +110,11 @@ enum acpi_gpio_io_restrict {
 	ACPI_GPIO_IO_RESTRICT_PRESERVE
 };
 
+enum acpi_gpio_polarity {
+	ACPI_GPIO_ACTIVE_HIGH = 0,
+	ACPI_GPIO_ACTIVE_LOW = 1,
+};
+
 #define ACPI_GPIO_REVISION_ID		1
 #define ACPI_GPIO_MAX_PINS 		8
 
@@ -129,13 +134,23 @@ struct acpi_gpio {
 	uint16_t output_drive_strength;		/* 1/100 mA */
 	int io_shared;
 	enum acpi_gpio_io_restrict io_restrict;
+	enum acpi_gpio_polarity polarity;
 };
 
 /* Basic output GPIO with default pull settings */
-#define ACPI_GPIO_OUTPUT(gpio) { \
+#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) { \
+	.type = ACPI_GPIO_TYPE_IO, \
+	.pull = ACPI_GPIO_PULL_DEFAULT, \
+	.io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \
+	.polarity = ACPI_GPIO_ACTIVE_HIGH,     \
+	.pin_count = 1, \
+	.pins = { (gpio) } }
+
+#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) { \
 	.type = ACPI_GPIO_TYPE_IO, \
 	.pull = ACPI_GPIO_PULL_DEFAULT, \
 	.io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \
+	.polarity = ACPI_GPIO_ACTIVE_LOW,     \
 	.pin_count = 1, \
 	.pins = { (gpio) } }
 
diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c
index 25e5104129..4a057b51d5 100644
--- a/src/drivers/generic/max98357a/max98357a.c
+++ b/src/drivers/generic/max98357a/max98357a.c
@@ -55,7 +55,8 @@ static void max98357a_fill_ssdt(struct device *dev)
 	/* This points to the first pin in the first gpio entry in _CRS */
 	path = acpi_device_path(dev);
 	dp = acpi_dp_new_table("_DSD");
-	acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, 0);
+	acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0,
+			 config->sdmode_gpio.polarity);
 	acpi_dp_add_integer(dp, "sdmode-delay", config->sdmode_delay);
 	acpi_dp_write(dp);
 
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index e1e926be00..25bd19d9d6 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -279,7 +279,7 @@ chip soc/intel/skylake
 		device pci 1f.2 on  end # Power Management Controller
 		device pci 1f.3 on
 			chip drivers/generic/max98357a
-				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_B2)"
+				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
 				device generic 0 on end
 			end
 		end # Intel HDA
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 087f85845e..43ec2ed054 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -84,7 +84,7 @@ chip soc/intel/apollolake
 		device pci 0d.3 on  end	# - Shared SRAM
 		device pci 0e.0 on	# - Audio
 			chip drivers/generic/max98357a
-				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT(GPIO_76)"
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
 				device generic 0 on end
 			end
 		end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index a5789b0bcd..8dded98470 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -303,7 +303,7 @@ chip soc/intel/skylake
 		device pci 1f.2 on  end # Power Management Controller
 		device pci 1f.3 on
 			chip drivers/generic/max98357a
-				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_E3)"
+				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
 				register "device_present_gpio" = "GPP_E3"
 				register "device_present_gpio_invert" = "1"
 				device generic 0 on end