summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2020-03-03 18:33:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-06 08:04:14 +0000
commit04b02069e26484caf2737a863404daf4a438714b (patch)
tree346e50a9ba16d31a2a075d85cec5ea76d3aaf282 /src
parent8e6fde0157b15b49131224a457a948f5a246f4d2 (diff)
downloadcoreboot-04b02069e26484caf2737a863404daf4a438714b.tar.xz
soc/intel/common/block/tco: clear TCO1_STS register, too
The register TCO1_STS is never cleared, which will cause SMIs to either retrigger over and over again (e.g. TIMEOUT) or prevent concurrent interrupt events, depending on which event triggered. Clear both TCO2_STS and TCO1_STS. This also fixes the issue where SECOND_TO_STS will always end up set in the SMI handler by unconditionally (re)setting it. Tested on X11SSM-F, where enabling TCO caused the terminal to get flooded with SMI debug messages. With this patch, a message gets written every ~1 second. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39259 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/common/block/smbus/tco.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index 1a215eb69d..bd8790aa6e 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -74,13 +74,13 @@ uint32_t tco_reset_status(void)
uint16_t tco1_sts;
uint16_t tco2_sts;
- /* TCO Status 2 register */
- tco2_sts = tco_read_reg(TCO2_STS);
- tco2_sts |= TCO_STS_SECOND_TO;
- tco_write_reg(TCO2_STS, tco2_sts);
-
/* TCO Status 1 register */
tco1_sts = tco_read_reg(TCO1_STS);
+ tco_write_reg(TCO1_STS, tco1_sts);
+
+ /* TCO Status 2 register */
+ tco2_sts = tco_read_reg(TCO2_STS);
+ tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO);
return (tco2_sts << 16) | tco1_sts;
}