diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-16 10:51:06 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-16 15:06:10 +0200 |
| commit | 084ed45a95a6afaf238572259e976d01320cf08b (patch) | |
| tree | aa9427305f28df95a3220c30510ea5daa2e40c9b /src | |
| parent | 16de28ae92ac05dcfb3963cf72c243f6dd4ca02d (diff) | |
| download | coreboot-084ed45a95a6afaf238572259e976d01320cf08b.tar.xz | |
gm45: Make UMA size configurable.
Change-Id: I27b2ec70b9c77f3caf9d52788f46f5dc16045d1b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6686
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/x200/cmos.layout | 11 | ||||
| -rw-r--r-- | src/mainboard/roda/rk9/cmos.layout | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/igd.c | 12 |
3 files changed, 30 insertions, 5 deletions
diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 83dd3c5c13..c668923ef0 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -104,7 +104,10 @@ entries 937 1 e 1 low_battery_beep 938 1 e 1 uwb -#939 5 r 0 unused +# coreboot config options: northbridge +939 3 e 11 gfx_uma_size + +#942 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -150,6 +153,12 @@ enumerations 9 1 Primary 10 0 AHCI 10 1 Compatible +11 0 32M +11 1 48M +11 2 64M +11 3 128M +11 5 96M +11 6 160M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index ca439c9288..f89fbc4e70 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -96,7 +96,11 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 unused + +# coreboot config options: northbridge +1000 3 e 10 gfx_uma_size + +#1003 21 r 0 unused # ram initialization internal data 1024 128 r 0 read_training_results @@ -136,6 +140,12 @@ enumerations 8 1 Yes 9 0 AHCI 9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M # ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 0a8f21e586..786919f08b 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> +#include <pc80/mc146818rtc.h> #include "gm45.h" @@ -40,6 +41,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) u16 reg16; u32 reg32; + u8 gfxsize; printk(BIOS_DEBUG, "Enabling IGD.\n"); @@ -61,12 +63,16 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) /* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ - /* Graphics Mode Select: 32MB framebuffer (0x0050) */ - /* TODO: We could switch to 64MB (0x0070), config flag? */ const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); reg16 = pci_read_config16(mch_dev, D0F0_GGC); + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 0 for 32MB */ + gfxsize = 0; + } + reg16 &= 0xf00f; - reg16 |= 0x0350; + reg16 |= 0x0300 | ((gfxsize + 5) << 4); if (!(capid & (1 << (48 - 32)))) reg16 |= 0x0800; pci_write_config16(mch_dev, D0F0_GGC, reg16); |