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authorDuncan Laurie <dlaurie@chromium.org>2013-05-28 07:55:02 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-25 23:48:22 +0100
commit116aa3a1900dae2beb56f381e91c9890c1e8ca30 (patch)
treec39a0a99c52805c1166d98c7defb0eca8ef06a6b /src
parentc7f2ab742b2589281efa852309e29c8da5270fbe (diff)
downloadcoreboot-116aa3a1900dae2beb56f381e91c9890c1e8ca30.tar.xz
falco: Add panel power sequence timings
These are placeholder values until we can configure for the exact panel. Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56808 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4197 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/falco/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index fc6462c2a2..b9bc47fb17 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -13,6 +13,14 @@ chip northbridge/intel/haswell
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end