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authorAndrey Petrov <anpetrov@fb.com>2020-04-30 13:37:12 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-05-01 23:11:55 +0000
commit15070e7ea86eefc211718b967e50fe44281bd879 (patch)
treea9f32bd927f9b9dbb3f42b80184f6b2569fec1b4 /src
parent26679699cddaccdc1539e5c0c4b82e49e7ec2900 (diff)
downloadcoreboot-15070e7ea86eefc211718b967e50fe44281bd879.tar.xz
soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs. Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/xeon_sp/include/soc/p2sb.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h
new file mode 100644
index 0000000000..b90bc73cc1
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <commonlib/helpers.h>
+
+/*
+ * Currently all known xeon-sp CPUs use C620 PCH. These definitions
+ * come from C620 datasheet (Intel Doc #336067-007US)
+ */
+
+#define HPTC_OFFSET 0x60
+#define HPTC_ADDR_ENABLE_BIT (1 << 7)
+#define PCH_P2SB_EPMASK0 0xb0
+#define P2SB_SIZE (16 * MiB)