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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-07 12:00:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-14 18:13:15 +0000 |
| commit | 1cfafe25e37d3a396a19bfe524af16284ff41070 (patch) | |
| tree | fa48bc17e9070649105b4ee48ffd7c20700e6332 /src | |
| parent | 7adc370dc79af1aacd6f811b9b28d01d595da702 (diff) | |
| download | coreboot-1cfafe25e37d3a396a19bfe524af16284ff41070.tar.xz | |
intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/romstage.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_init.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 2 |
5 files changed, 7 insertions, 6 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b1da177281..5b8d1d811e 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1723,9 +1723,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) while (!(read8((u8 *)0xfed40000) & (1 << 7))) {} } - /* Enable SMBUS. */ - enable_smbus(); - /* Collect information about DIMMs and find common settings. */ collect_dimm_config(sysinfo); diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index eae87f3674..26d336bfd2 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,8 +34,6 @@ void mainboard_romstage_entry(void) u8 boot_path = 0; u8 s3_resume; - enable_smbus(); - #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) i82801jx_early_init(); #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 92db7d833c..4ce4fbebc4 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -23,6 +23,9 @@ void i82801ix_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + if (ENV_ROMSTAGE) + enable_smbus(); + /* Set up RCBA. */ pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 1afc6b365f..87831bbd05 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -81,6 +81,9 @@ void i82801jx_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + if (ENV_ROMSTAGE) + enable_smbus(); + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801jx_setup_bars(); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 26a99f42f7..2c5135ebfd 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -225,8 +225,8 @@ static inline int lpc_is_mobile(const u16 devid) } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -#if ENV_ROMSTAGE void enable_smbus(void); +#if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); |