summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-07 18:13:47 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-25 10:22:33 +0000
commit1fb17d65cfa0877577239767757ae27d2625d74c (patch)
treeedb52242dc1fabc4780bfe47899f89a518fc5c79 /src
parent31929bf48968845e9824cc0fb37b1bf0e9f7dd77 (diff)
downloadcoreboot-1fb17d65cfa0877577239767757ae27d2625d74c.tar.xz
soc/intel/baytrail/cpu.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/cpu.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index f745b32b1f..0f48bde8e4 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -13,14 +13,13 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <reg_script.h>
-
#include <soc/iosf.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/ramstage.h>
/* Core level MSRs */
-const struct reg_script core_msr_script[] = {
+static const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
@@ -31,7 +30,7 @@ const struct reg_script core_msr_script[] = {
REG_SCRIPT_END
};
-static void baytrail_core_init(struct device *cpu)
+static void soc_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
@@ -54,7 +53,7 @@ static void baytrail_core_init(struct device *cpu)
}
static struct device_operations cpu_dev_ops = {
- .init = baytrail_core_init,
+ .init = soc_core_init,
};
static const struct cpu_device_id cpu_table[] = {