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authorPeichao Wang <peichao.wang@bitland.corp-partner.google.com>2019-12-31 11:24:13 +0800
committerMartin Roth <martinroth@google.com>2020-01-07 15:44:53 +0000
commit2f72a204a79729d77308ae12c0e9eaf0c329f366 (patch)
treecb7fdcb4cc0eb6b7f70a561e7eef62762bef67a4 /src
parente938fb78f9e866911ddccecdd929f3ecb1ebed3b (diff)
downloadcoreboot-2f72a204a79729d77308ae12c0e9eaf0c329f366.tar.xz
mb/google/kahlee/treeya: tune eDP delay time to 20 ms
tune eDP delay time to 20 ms ensure satisfy panel spec BUG=b:147270512 TEST=verify panel sequences by ODM. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/kahlee/variants/treeya/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
index e35f00c380..019dcf65ed 100644
--- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
@@ -23,6 +23,8 @@ chip soc/amd/stoneyridge
register "stapm_percent" = "68"
register "stapm_time_ms" = "900000"
register "stapm_power_mw" = "7800"
+ register "lvds_poseq_varybl_to_blon" = "0x5"
+ register "lvds_poseq_blon_to_varybl" = "0x5"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{