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authorPatrick Rudolph <siro@das-labor.org>2015-06-24 19:14:53 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-28 22:40:41 +0200
commit3247916d1105a33a1c93be415e3bcded785c86cf (patch)
tree27ef529915761cfd7eb782f3f547420bd6ddbdda /src
parent039edebc08fb8238a027a1f2277278cf1fde65b9 (diff)
downloadcoreboot-3247916d1105a33a1c93be415e3bcded785c86cf.tar.xz
intel raminit: properly handle DDR3 DIMMs with address mirroring
Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10652 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index a5694118d1..e567ccee02 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -812,7 +812,6 @@ static void dram_timing_regs(ramctr_timing * ctrl)
static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl)
{
- int t;
u32 reg, val32;
int channel;
@@ -832,11 +831,6 @@ static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl)
dimmA = &info->dimm[channel][1];
dimmB = &info->dimm[channel][0];
reg |= (1 << 16);
- // swap dimm info
- t = ctrl->rank_mirror[channel][1];
- ctrl->rank_mirror[channel][1] =
- ctrl->rank_mirror[channel][3];
- ctrl->rank_mirror[channel][3] = t;
}
// dimmA
if (dimmA && (dimmA->ranks > 0)) {
@@ -1231,6 +1225,9 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank,
printram("MRd: %x <= %x\n", reg, val);
if (ctrl->rank_mirror[channel][slotrank]) {
+ /* DDR3 Rank1 Address mirror
+ * swap the following pins:
+ * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */
reg = ((reg >> 1) & 1) | ((reg << 1) & 2);
val = (val & ~0x1f8) | ((val >> 1) & 0xa8)
| ((val & 0xa8) << 1);