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authorDuncan Laurie <dlaurie@chromium.org>2016-09-19 17:24:55 -0700
committerPatrick Georgi <pgeorgi@google.com>2016-09-21 10:47:02 +0200
commit401bd31b2d9efed119d82eb4c153bd273fe64b49 (patch)
treea3d6d8fcb9c9818522fb0848d3f0e2f257d331e1 /src
parent94cc485338a30c50c74a7bb02d14a52f35ff41c3 (diff)
downloadcoreboot-401bd31b2d9efed119d82eb4c153bd273fe64b49.tar.xz
mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16673 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/reef/Kconfig4
-rw-r--r--src/mainboard/google/reef/variants/baseboard/gpio.c1
2 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 0013ffd897..5039725727 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
select I2C_TPM
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_TPM2
+ select MAINBOARD_HAS_I2C_TPM_CR50
select TPM2
if BOARD_GOOGLE_BASEBOARD_REEF
@@ -24,6 +25,9 @@ config DRIVER_TPM_I2C_BUS
config DRIVER_TPM_I2C_ADDR
hex "0x50"
+config DRIVER_TPM_I2C_IRQ
+ int "60" # GPE0_DW1_28
+
config CHROMEOS
select LID_SWITCH if BASEBOARD_REEF_LAPTOP
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index 7d74140c78..976a5040f2 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -353,6 +353,7 @@ static const struct pad_config early_gpio_table[] = {
/* I2C2 - TPM */
PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
};