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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-09-18 17:26:36 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-21 14:47:53 +0000 |
| commit | 402276574b9812c0e2d527ed50a3392439a97919 (patch) | |
| tree | 1aee5a2e9804bfefebaf58f7654550a7d9e1ffca /src | |
| parent | 841416f6f8318f65982c29d376fce2e810045b8d (diff) | |
| download | coreboot-402276574b9812c0e2d527ed50a3392439a97919.tar.xz | |
siemens/mc_apl1: Move SCI to IRQ 10
IRQ 9 is used for different purpose on this mainboard so move SCI away
to IRQ 10.
Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index 7f4983e512..04b3ae5286 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -4,6 +4,8 @@ chip soc/intel/apollolake device lapic 0 on end end + register "sci_irq" = "SCIS_IRQ10" + # Disable unused clkreq of PCIe root ports register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" |