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authorNico Huber <nico.huber@secunet.com>2013-10-22 11:07:23 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2014-07-11 09:23:56 +0200
commit40f9ce93fa1d9e5206cd5c1081d22c60bfc6d3f3 (patch)
tree8b50c7f29d62130ffa27aa6a05424995213750d1 /src
parent2b2f849b537db935453694e863f9b4f73efbbff5 (diff)
downloadcoreboot-40f9ce93fa1d9e5206cd5c1081d22c60bfc6d3f3.tar.xz
kontron/ktqm77: Improve W83627DHG's GPIO config
Fix some outputs of the super i/o that should be GPIOs and make variables out of magic values that configure LVDS. Change-Id: Ib9eef065980cefff0046485549a68cf8f070d5b9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6248 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/kontron/ktqm77/romstage.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 09fd634606..d74f3a6da3 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -140,13 +140,22 @@ static void pnp_exit_ext_func_mode(device_t dev)
static void superio_gpio_config(void)
{
+ int lvds_3v = 0; // 0 (5V) or 1 (3V3)
+ int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled
device_t dev = PNP_DEV(0x2e, 0x9);
pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
+ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
+ pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are
+ GPIO27, 26, 25, 24 */
+ pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32,
+ Pins 78~85 are UART B */
+ pnp_write_config(dev, 0x2d, 0x00); /* Pins 67, 68, 70~73, 75, 77 are
+ GPIO57~50 */
pnp_set_logical_device(dev);
/* Values can only be changed, when devices are enabled. */
- pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */
- pnp_write_config(dev, 0xe4, 0x22); /* GPIO2 bits 1, 5 are 1 */
+ pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */
pnp_exit_ext_func_mode(dev);
}