diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2015-06-25 19:32:28 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-28 22:42:11 +0200 |
| commit | 4275ff86fa09ad725b082d4387d75c78888bbda5 (patch) | |
| tree | b969c1ecd0c4a1e499b3ea26211481cfda2d86d9 /src | |
| parent | 3247916d1105a33a1c93be415e3bcded785c86cf (diff) | |
| download | coreboot-4275ff86fa09ad725b082d4387d75c78888bbda5.tar.xz | |
intel raminit: check correct registers in channel_test
Found while doing code review. No actual problem was observed.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Verify byte-lane error count registers 0 to 7 instead of verifying byte-lane
error count register 0 eight times in a row.
Change-Id: Ife6ac6558b2f65ad947870cde5f15d90560ce6d9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10664
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e567ccee02..8d1feccb75 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -3392,7 +3392,7 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10))) + if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) die("Mini channel test failed (2)\n"); } } |