summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2015-08-05 17:01:55 +0530
committerMartin Roth <martinroth@google.com>2016-01-14 19:17:01 +0100
commit45a221de7923d6c1d52f9ca14a3419e7d0803636 (patch)
treee3f742125a2939b6a035720ccb2b5820934b375c /src
parentbaf00e6b28efcf02497a566fa6f0f43d11304406 (diff)
downloadcoreboot-45a221de7923d6c1d52f9ca14a3419e7d0803636.tar.xz
soc/braswell: Fix P-state table
Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/braswell/include/soc/msr.h3
-rw-r--r--src/soc/intel/braswell/include/soc/pattrs.h2
-rw-r--r--src/soc/intel/braswell/ramstage.c2
-rw-r--r--src/soc/intel/braswell/tsc_freq.c32
4 files changed, 33 insertions, 6 deletions
diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 93701aad75..d998e68dd8 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -43,6 +43,7 @@
#define MSR_CPU_THERM_CFG2 0x674
#define MSR_CPU_THERM_SENS_CFG 0x675
-#define BUS_FREQ_KHZ 100000 /* 100 MHz */
+/* Read BCLK from MSR */
+unsigned int cpu_bus_freq_khz(void);
#endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h
index 439d0bd8d9..d86f9ee98e 100644
--- a/src/soc/intel/braswell/include/soc/pattrs.h
+++ b/src/soc/intel/braswell/include/soc/pattrs.h
@@ -44,7 +44,7 @@ struct pattrs {
const void *microcode_patch;
int address_bits;
int num_cpus;
- unsigned bclk_khz;
+ unsigned int bclk_khz;
};
/*
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 749feaff52..1e085d7e93 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -128,7 +128,7 @@ static void fill_in_pattrs(void)
attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
/* Set bus clock speed */
- attrs->bclk_khz = BUS_FREQ_KHZ;
+ attrs->bclk_khz = cpu_bus_freq_khz();
}
static inline void set_acpi_sleep_type(int val)
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index 284ba2b23e..fff882eb9b 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -26,12 +26,38 @@
#endif
#include <stdint.h>
+static const unsigned int cpu_bus_clk_freq_table[] = {
+ 83333,
+ 100000,
+ 133333,
+ 116666,
+ 80000,
+ 93333,
+ 90000,
+ 88900,
+ 87500
+};
+
+unsigned int cpu_bus_freq_khz(void)
+{
+ msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+ if((clk_info.lo & 0xF) < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
+ {
+ return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]);
+ }
+ return 0;
+}
+
unsigned long tsc_freq_mhz(void)
{
- msr_t ia_core_ratios;
+ msr_t platform_info;
+ unsigned int bclk_khz = cpu_bus_freq_khz();
+
+ if (!bclk_khz)
+ return 0;
- ia_core_ratios = rdmsr(MSR_IACORE_RATIOS);
- return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000;
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+ return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
}
#if !ENV_SMM