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authorNaresh G Solanki <naresh.solanki@intel.com>2016-10-27 21:18:25 +0530
committerAaron Durbin <adurbin@chromium.org>2016-11-03 17:45:39 +0100
commit46575fb1d4f00e0d1e69e9ad38acb4c1e4b38711 (patch)
tree677084da5a42cf6a8cad962bef0c36d83e34ee29 /src
parentcebf64592702185be0eba4e4b44f1a9c258751fc (diff)
downloadcoreboot-46575fb1d4f00e0d1e69e9ad38acb4c1e4b38711.tar.xz
mainboard/intel/kblrvp: Update onboard memory specific configs
1. Update dq, dqs map & Rcomp strength & Rcomp target. 2. Fix rvp3.spd.hex byte 2 to 0x0F(JEDEC LPDDR3 memory type). Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/kblrvp/spd/rvp3.spd.hex4
-rw-r--r--src/mainboard/intel/kblrvp/spd/spd_util.c8
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
index e032411713..9be32983f5 100644
--- a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
+++ b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
@@ -1,4 +1,4 @@
-24 20 F1 0E 14 11 95 00 00 00 00 03 0B 23 00 00
+24 20 0F 0E 14 11 95 00 00 00 00 03 0B 23 00 00
00 00 0A FF 54 00 00 00 78 00 90 A8 90 10 04 E0
01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -13,4 +13,4 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
index 68bdb48b6b..dc042d4b1a 100644
--- a/src/mainboard/intel/kblrvp/spd/spd_util.c
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -28,8 +28,8 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr)
const u8 dq_map[2][12] = {
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
- 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}
@@ -37,8 +37,8 @@ void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
- { 0, 1, 3, 2, 6, 5, 4, 7 },
- { 2, 3, 0, 1, 6, 7, 4, 5 } };
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
}