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authorSubrata Banik <subrata.banik@intel.com>2017-07-17 16:45:54 +0530
committerMartin Roth <martinroth@google.com>2017-07-18 19:07:52 +0000
commit48f96739edbe8d532e0d74c32e11fe422d44e02c (patch)
tree7b41faf0993881360ebd3981131939ed49bdc08a /src
parenta271b1d13dbc360d8c856289b93d269a015c83a0 (diff)
downloadcoreboot-48f96739edbe8d532e0d74c32e11fe422d44e02c.tar.xz
soc/intel/skylake: Remove Heci2 and Heci3 from wake resource list
HECI2 and HECI3 devices are “function disable” during FSP Silicon Init phase. Device will not be visible over PCI bus hence removing these devices from wake source list. Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/elog.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index fde8be2f7d..1178e80ff8 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -216,8 +216,6 @@ static void pch_log_pme_internal_wake_source(void)
{ PCH_DEVFN_PCIE12, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE12 },
{ PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },
{ PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },
- { PCH_DEVFN_CSE_2, 0x54, ELOG_WAKE_SOURCE_PME_CSE2 },
- { PCH_DEVFN_CSE_3, 0x54, ELOG_WAKE_SOURCE_PME_CSE3 },
{ PCH_DEVFN_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },
{ PCH_DEVFN_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },
};