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authorStefan Reinauer <reinauer@chromium.org>2014-02-19 15:05:15 -0800
committerPatrick Georgi <patrick@georgi-clan.de>2014-07-12 20:17:03 +0200
commit4923c399f3ca1120aba3f4d5e16eaa2b815ea2aa (patch)
tree6a94dc7be1879f278fb3a43f13af72f86ce935c3 /src
parentc63ad997a5e4614cfb12f3d1743e86b21e6e31af (diff)
downloadcoreboot-4923c399f3ca1120aba3f4d5e16eaa2b815ea2aa.tar.xz
google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled" Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6007 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/panther/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 9fbe8e62b3..7cc3672f84 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -61,6 +61,9 @@ chip northbridge/intel/haswell
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
+ # Force enable ASPM for PCIe Port 4
+ register "pcie_port_force_aspm" = "0x10"
+
# Enable port coalescing
register "pcie_port_coalesce" = "1"