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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 03:00:24 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:09:34 +0000 |
| commit | 4d962b2ecf25c82987a3456160c4566da34946d7 (patch) | |
| tree | 6e7aa8b23e75585c131cbb51fe80f79eee59cdd8 /src | |
| parent | f67bf49ead50ca07e6483b8b209ee1ab1bfa1e7e (diff) | |
| download | coreboot-4d962b2ecf25c82987a3456160c4566da34946d7.tar.xz | |
nb/intel/pineview: Tidy up comments and cosmetics
Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/pineview/acpi/hostbridge.asl | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/acpi/peg.asl | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/acpi/pineview.asl | 4 |
3 files changed, 9 insertions, 14 deletions
diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 434ed07176..0a9897c69d 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -24,7 +24,7 @@ Device (MCHC) , 13, MHBR, 22, /* MCHBAR */ - Offset (0x60), /* PCIec BAR */ + Offset (0x60), /* PCIe BAR */ PXEN, 1, /* Enable */ PXSZ, 2, /* BAR size */ , 23, @@ -35,7 +35,7 @@ Device (MCHC) , 11, /* DMBR, 20, /* DMIBAR */ - // ... + /* ... */ Offset (0x90), /* PAM0 */ , 4, @@ -73,18 +73,14 @@ Device (MCHC) , 2, Offset (0xa0), /* Top of Memory */ - TOM, 8, + TOM, 8, Offset (0xb0), /* Top of Low Used Memory */ , 4, TLUD, 12, - } - } - -/* Current Resource Settings */ Name (MCRS, ResourceTemplate() { /* Bus Numbers */ @@ -199,6 +195,7 @@ Name (MCRS, ResourceTemplate() 0x00005000,,, TPMR) }) +/* Current Resource Settings */ Method (_CRS, 0, Serialized) { /* Find PCI resource area in MCRS */ @@ -206,7 +203,8 @@ Method (_CRS, 0, Serialized) CreateDwordField(MCRS, ^PM01._MAX, PMAX) CreateDwordField(MCRS, ^PM01._LEN, PLEN) - /* Fix up PCI memory region: + /* + * Fix up PCI memory region: * Enter actual TOLUD. The TOLUD register contains bits 27-31 of * the top of memory address. */ diff --git a/src/northbridge/intel/pineview/acpi/peg.asl b/src/northbridge/intel/pineview/acpi/peg.asl index f85a22c08b..6a67238317 100644 --- a/src/northbridge/intel/pineview/acpi/peg.asl +++ b/src/northbridge/intel/pineview/acpi/peg.asl @@ -12,16 +12,15 @@ Device (PEGP) Package() { 0x0000ffff, 0, 0, 16 }, Package() { 0x0000ffff, 1, 0, 17 }, Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } + Package() { 0x0000ffff, 3, 0, 19 }, }) } Else { Return (Package() { Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, }) } - } } diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 074e9007d7..3579a260b9 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -10,9 +10,7 @@ Device (PDRC) Name (_HID, EISAID("PNP0C02")) Name (_UID, 1) - /* This does not seem to work correctly yet - set values statically for - * now. - */ + /* This does not seem to work correctly yet - set values statically for now. */ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) |